CKSTPR2—Clock Stop Register 2
Bit
7
—
Initial value
1
Read/Write
—
6
5
—
—
1
1
—
—
PWM module standby mode control
0 PWM is set to module standby mode
1
WDT module standby mode control
0 WDT is set to module standby mode
1
WDT module standby mode is cleared
Asynchronous event counter module standby mode control
0 Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
Appendix B Internal I/O Registers
H'FB
4
3
—
AECKSTP
WDCKSTP
1
1
—
R/W
LCD module standby mode control
0 LCD is set to module standby mode
1
LCD module standby mode is cleared
PWM module standby mode is cleared
Rev. 6.00 Aug 04, 2006 page 629 of 680
System control
2
1
PWCKSTP
LDCKSTP
1
1
R/W
R/W
R/W
REJ09B0145-0600
0
1