Table 15.28 Serial Interface (Sci1) Timing - Renesas H8/3847R Series Hardware Manual

Section 15 Electrical Characteristics
Item Symbol
Input pin low t
IL
width
UD pin minimum t
UDH
transition width t
UDL
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. The figure in parentheses ( ) indicates the maximum fosc value when an external clock
is used.
3. Also applies to H8/38347 Group.
4. Also applies to H8/38447 Group.

Table 15.28 Serial Interface (SCI1) Timing

V = 2.7 V to 5.5 V, AV
CC
Item Symbol Pins
Input clock cycle t
Scyc
Input clock high t
SCKH
width
Input clock low t
SCKL
width
Input clock rise t
SCKr
time
Input clock fall t
SCKf
time
Serial output t
SOD
data delay time
Serial input data t
SIS
setup time
Serial input data t
SIH
hold time
Rev. 6.00 Aug 04, 2006 page 528 of 680
REJ09B0145-0600
Applicable
Min
Pins
IRQ0
to 2
0
IRQ0
,
4
WKP
to
0
WKP
,
7
ADTRG,
TMIC,
TMIF, TMIG,
AEVL, AEVH
UD 4
= 2.7 V to 5.5 V, V
CC
Values
Applicable
Min Typ
SCK 4 —
1
SCK 0.4 —
1
SCK 0.4 —
1
SCK — —
1
SCK — —
1
SO — —
1
SI 200.0 —
1
SI 200.0 —
1
Values
Typ Max Unit
— — t
cyc
t
subcyc
— — t
cyc
t
subcyc
= AV = 0.0 V unless otherwise indicated
SS SS
Max Unit Test Condition
— t
cyc
— t
Scyc
— t
Scyc
60.0 ns
60.0 ns
200.0 ns
— ns
— ns
Reference
Test Condition
Figure
Figure
15.3
Figure
15.4
Reference
Figure
Figure 15.5
Figure 15.5
Figure 15.5
Figure 15.5 *
Figure 15.5 *
Figure 15.5 *
Figure 15.5 *
Figure 15.5 *