Register Descriptions; Table 9.11 Pin Configuration; Table 9.12 Timer G Registers - Renesas H8/3847R Series Hardware Manual

Section 9 Timers
3. Pin Configuration
Table 9.11 shows the timer G pin configuration.

Table 9.11 Pin Configuration

Name
Input capture input
4. Register Configuration
Table 9.12 shows the register configuration of timer G.

Table 9.12 Timer G Registers

Name
Timer control register G
Timer counter G
Input capture register GF
Input capture register GR
Clock stop register 1
9.5.2

Register Descriptions

1. Timer Counter (TCG)
7
Bit:
TCG7
Initial value: 0
Read/Write:
—
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
Rev. 6.00 Aug 04, 2006 page 296 of 680
REJ09B0145-0600
Abbr. I/O
TMIG Input
Abbr.
TMG
TCG
ICRGF
ICRGR
CKSTPR1
6 5
TCG6 TCG5 TCG4
0 0
— —
Function
Input capture input pin
R/W Initial Value
R/W H'00
— H'00
R H'00
R H'00
R/W H'FF
4 3
TCG3 TCG2
0 0
— — —
Address
H'FFBC
—
H'FFBD
H'FFBE
H'FFFA
2 1 0
TCG1 TCG0
0 0 0
— —