Renesas H8/3847R Series Hardware Manual page 618

Appendix B Internal I/O Registers
SCSR1—Serial Control Status Register 1
Bit 7

Initial value 1

Read/Write
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Aug 04, 2006 page 580 of 680
REJ09B0145-0600
6 5

SOL ORER
0 0

R/W R/(W)
*
Start flag
0
1
Tail mark transmission flag
0 Idle state, or 8-bit/16-bit data transfer in progress
1 Tail mark transmission in progress
Overrun error flag
0 [Clearing condition]
After reading ORER = 1, cleared by writing 0 to ORER
1 [Setting condition]
When an external clock is used and the clock is input
after transfer is completed
Extension data bit
0 Read SO pin output level is low
1
Write Changes SO
1 Read SO pin output level is high
1
Write Changes SO
H'A1
4 3 2
 
1 1 1
 
Read Transfer operation stopped
Write Invalid
Read Transfer operation in progress
Write Starts transfer operation
pin output to low level
1
pin output to high level
1
SCI1
1 0
MTRF STF
0 0
R R/W