Renesas H8/3847R Series Hardware Manual page 400

Section 10 Serial Communication Interface
Bit 5: Overrun error (OER)
Bit 5 indicates that an overrun error has occurred during reception.
Bit 5
OER Description
Reception in progress or completed *
0
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
An overrun error has occurred during reception *
1
Setting condition:
When reception is completed with RDRF set to 1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.
Bit 4: Framing error (FER)
Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4
FER Description
Reception in progress or completed *
0
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1 A framing error has occurred during reception
Setting condition:
When the stop bit at the end of the receive data is checked for a value
of 1 at the end of reception, and the stop bit is 0 *
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit
FER set to 1. In synchronous mode, neither transmission nor reception is possible
when bit FER is set to 1.
Rev. 6.00 Aug 04, 2006 page 362 of 680
REJ09B0145-0600
1
2
1
2
(initial value)
(initial value)