Item
Symbol Pins
Input pin low
t
IL
width
UD pin minimum
t
UDH
modulation width
t
UDL
Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
2. When internal power supply step-down circuit is not used.
3. Figures in parentheses are the maximum t
Values
Applicable
Min
Typ
IRQ
to IRQ
,
2
—
0
4
WKP
to
0
WKP
,
7
ADTRG,
TMIC, TMIF,
TMIG, AEVL,
AEVH
UD
4
—
Section 15 Electrical Characteristics
Max
Unit
Test Condition
—
t
cyc
t
subcyc
—
t
cyc
t
subcyc
rate with external clock input.
OSC
Rev. 6.00 Aug 04, 2006 page 491 of 680
Reference
Figure
Figure 15.3
Figure 15.4
REJ09B0145-0600