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Mnemonic
JMP @Rn
JMP @aa:16
JMP @@aa:8
BSR d:8
JSR @Rn
JSR @aa:16
JSR @@aa:8
RTS
RTE
SLEEP
LDC #xx:8, CCR
LDC Rs, CCR
STC CCR, Rd
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
EEPMOV
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
Operation
— PC ← Rn16
— PC ← aa:16
— PC ← @aa:8
— SP–2 → SP
PC → @SP
PC ← PC+d:8
— SP–2 → SP
PC → @SP
PC ← Rn16
— SP–2 → SP
PC → @SP
PC ← aa:16
SP–2 → SP
PC → @SP
PC ← @aa:8
— PC ← @SP
SP+2 → SP
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
— Transit to sleep mode.
B #xx:8 → CCR
B Rs8 → CCR
B CCR → Rd8
B CCR∧#xx:8 → CCR
B CCR∨#xx:8 → CCR
B CCR⊕#xx:8 → CCR
— PC ← PC+2
— if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
Appendix A CPU Instruction Set
Addressing Mode/
Instruction Length (bytes) Condition Code
2
4
2
2
2
4
2
2
2
2
2
2
2
Rev. 6.00 Aug 04, 2006 page 549 of 680
I
H N Z V C
— — — — — — 4
— — — — — — 6
— — — — — — 8
— — — — — — 6
— — — — — — 6
— — — — — — 8
— — — — — — 8
2 — — — — — — 8
2
1
0
2 — — — — — — 2
2
2
— — — — — — 2
2
2
2
2 — — — — — — 2
4 — — — — — — (4)
REJ09B0145-0600
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