Register Descriptions; Table 9.20 Asynchronous Event Counter Registers - Renesas H8/3847R Series Hardware Manual

Section 9 Timers
4. Register Configuration
Table 9.20 shows the register configuration of the asynchronous event counter.

Table 9.20 Asynchronous Event Counter Registers

Name
Event counter control/status register
Event counter H
Event counter L
Clock stop register 2
9.7.2

Register Descriptions

1. Event Counter Control/Status Register (ECCSR)
Bit 7
OVH
Initial Value 0
Read/Write R/(W) *
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Rev. 6.00 Aug 04, 2006 page 322 of 680
REJ09B0145-0600
Abbr.
ECCSR
ECH
ECL
CKSTP2
6 5
OVL —
0 0
R/(W) *
R/W
R/W Initial Value
R/W H'00
R H'00
R H'00
R/W H'FF
4 3
CH2 CUEH CUEL
0 0
R/W R/W R/W
Address
H'FF95
H'FF96
H'FF97
H'FFFB
2 1 0
CRCH CRCL
0 0 0
R/W R/W