Renesas H8/3847R Series Hardware Manual page 32

Section 1 Overview
Table 1.1 Features ..................................................................................................................
Table 1.2 Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version) .................. 13
Table 1.3 Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version) .................. 18
Table 1.4 Bonding Pad Coordinates of HCD64F38347 and HCD64F38447......................... 23
Table 1.5 Bonding Pad Coordinates of H8/38347 Group (Mask ROM Version)
and H8/38447 Group (Mask ROM Version) .......................................................... 28
Table 1.6 Pin Functions.......................................................................................................... 32
Section 2 CPU
Table 2.1 Addressing Modes.................................................................................................. 47
Table 2.2 Effective Address Calculation................................................................................ 50
Table 2.3 Instruction Set ........................................................................................................ 53
Table 2.4 Data Transfer Instructions ...................................................................................... 55
Table 2.5 Arithmetic Instructions........................................................................................... 57
Table 2.6 Logic Operation Instructions.................................................................................. 58
Table 2.7 Shift Instructions .................................................................................................... 59
Table 2.8 Bit-Manipulation Instructions ................................................................................ 61
Table 2.9 Branching Instructions ........................................................................................... 65
Table 2.10 System Control Instructions ................................................................................... 67
Table 2.11 Block Data Transfer Instruction ............................................................................. 68
Table 2.12 Registers with Shared Addresses............................................................................ 90
Table 2.13 Registers with Write-Only Bits .............................................................................. 91
Section 3 Exception Handling
Table 3.1 Exception Handling Types and Priorities............................................................... 93
Table 3.2 Interrupt Sources and Their Priorities .................................................................... 96
Table 3.3 Interrupt Control Registers ..................................................................................... 97
Table 3.4 Interrupt Wait States............................................................................................... 113
Table 3.5 Conditions Under which Interrupt Request Flag is Set to 1 ................................... 116
Section 5 Power-Down Modes
Table 5.1 Operating Modes .................................................................................................... 131
Table 5.2 Internal State in Each Operating Mode .................................................................. 133
Table 5.3 System Control Registers ....................................................................................... 134
Table 5.4 Clock Frequency and Settling Time (Times are in ms) .......................................... 141
Table 5.5 Setting and Clearing Module Standby Mode by Clock Stop Register.................... 153
Rev. 6.00 Aug 04, 2006 page xxx of xxxvi
Tables
2