Renesas H8/3847R Series Hardware Manual page 301

2. Timer Counter A (TCA)
Bit 7
TCA7
Initial value 0
Read/Write R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
3. Clock Stop Register 1 (CKSTPR1)
Bit: 7
S1CKSTP
Initial value: 1
Read/Write: R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer A is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 0: Timer A module standby mode control (TACKSTP)
Bit 0 controls setting and clearing of module standby mode for timer A.
TACKSTP Description
0 Timer A is set to module standby mode
1 Timer A module standby mode is cleared
6 5
TCA6 TCA5
0 0
R R
6 5
S31CKSTP S32CKSTP ADCKSTP TGCKSTP
1 1
R/W R/W
4 3
TCA4 TCA3 TCA2
0 0
R R
4 3
TFCKSTP TCCKSTP TACKSTP
1 1
R/W R/W R/W
Rev. 6.00 Aug 04, 2006 page 263 of 680
Section 9 Timers
2 1 0
TCA1 TCA0
0 0 0
R R R
2 1
1 1
R/W R/W
(initial value)
REJ09B0145-0600
0
1