Sign In
Upload
Manuals
Brands
Renesas Manuals
Computer Hardware
H8/3844S
Renesas H8/3844S Manuals
Manuals and User Guides for Renesas H8/3844S. We have
1
Renesas H8/3844S manual available for free PDF download: Hardware Manual
Renesas H8/3844S Hardware Manual (721 pages)
8-Bit Single-Chip Microcomputer Super Low Power
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.94 MB
Table of Contents
Table of Contents
13
Section 1 Overview
39
Overview
39
Table 1.1 Features
40
Section 1 Overview
45
Internal Block Diagram
45
Figure 1.1 (1) Block Diagram (H8/3847R Group and H8/3847S Group)
45
Section 1 Overview
45
Figure 1.1 (2) Block Diagram (H8/38347 Group and H8/38447 Group)
46
Pin Arrangement and Functions
47
Pin Arrangement
47
Figure 1.2 Pin Arrangement (FP-100B, TFP-100B and TFP-100G: Top View)
48
Figure 1.3 Pin Arrangement (FP-100A: Top View)
49
Figure 1.4 Bonding Pad Location Diagram of H8/3847R Group (Mask ROM Version) (Top View)
50
Table 1.2 Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version)
51
Figure 1.5 Bonding Pad Location Diagram of H8/3847S Group (Mask ROM Version)
55
Table 1.3 Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version)
56
Figure 1.6 Bonding Pad Location Diagram of HCD64F38347 and HCD64F38447 (Top View)
60
Table 1.4 Bonding Pad Coordinates of HCD64F38347 and HCD64F38447
61
Figure 1.7 Bonding Pad Location Diagram of H8/38347 Group (Mask ROM Version)
65
Table 1.5 Bonding Pad Coordinates of H8/38347 Group (Mask ROM Version) and H8/38447 Group (Mask ROM Version)
66
Pin Functions
70
Table 1.6 Pin Functions
70
Section 2 CPU
77
Overview
77
Features
77
Address Space
78
Register Configuration
79
Figure 2.1 CPU Registers
79
Section 2 CPU
79
Register Descriptions
80
General Registers
80
Control Registers
80
Figure 2.2 Stack Pointer
80
Initial Register Values
82
Data Formats
82
Data Formats in General Registers
83
Figure 2.3 Register Data Formats
83
Memory Data Formats
84
Figure 2.4 Memory Data Formats
84
Section 2 CPU
85
Addressing Modes
85
Table 2.1 Addressing Modes
85
Effective Address Calculation
87
Table 2.2 Effective Address Calculation
88
Instruction Set
91
Table 2.3 Instruction Set
91
Data Transfer Instructions
93
Table 2.4 Data Transfer Instructions
93
Figure 2.5 Data Transfer Instruction Codes
94
Arithmetic Operations
95
Table 2.5 Arithmetic Instructions
95
Logic Operations
96
Table 2.6 Logic Operation Instructions
96
Shift Operations
97
Table 2.7 Shift Instructions
97
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
98
Bit Manipulations
99
Table 2.8 Bit-Manipulation Instructions
99
Figure 2.7 Bit Manipulation Instruction Codes
101
Branching Instructions
103
Table 2.9 Branching Instructions
103
Figure 2.8 Branching Instruction Codes
104
System Control Instructions
105
Table 2.10 System Control Instructions
105
Block Data Transfer Instruction
106
Figure 2.9 System Control Instruction Codes
106
Table 2.11 Block Data Transfer Instruction
106
Figure 2.10 Block Data Transfer Instruction Code
107
Basic Operational Timing
108
Access to On-Chip Memory (RAM, ROM)
108
Figure 2.11 On-Chip Memory Access Cycle
108
Access to On-Chip Peripheral Modules
109
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
109
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
110
CPU States
111
Overview
111
Figure 2.14 CPU Operation States
112
Program Execution State
113
Program Halt State
113
Exception-Handling State
113
Figure 2.15 State Transitions
113
Memory Map
114
Figure 2.16 (1) H8/3842R, H8/38342 and H8/38442 Memory Map
115
Figure 2.16 (2) H8/3843R, H8/38343 and H8/38443 Memory Map
116
Figure 2.16 (3) H8/3844R, H8/3844S, H8/38344 and H8/38444 Memory Map
117
Figure 2.16 (4) H8/3845R, H8/3845S, H8/38345 and H8/38445 Memory Map
118
Figure 2.16 (5) H8/3846R, H8/3846S, H8/38346 and H8/38446 Memory Map
119
Figure 2.16 (6) H8/3847R, H8/3847S, H8/38347 and H8/38447 Memory Map
120
Application Notes
121
Notes on Data Access
121
Figure 2.17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules
122
Notes on Bit Manipulation
123
Figure 2.18 Timer Configuration Example
124
Table 2.12 Registers with Shared Addresses
128
Table 2.13 Registers with Write-Only Bits
129
Notes on Use of the EEPMOV Instruction
130
Section 3 Exception Handling
131
Overview
131
Reset
131
Reset Sequence
131
Interrupt Immediately after Reset
132
Figure 3.1 Reset Sequence
132
Section 3 Exception Handling
132
Interrupts
133
Overview
133
Table 3.1 Exception Handling Types and Priorities
134
Table 3.2 Interrupt Sources and Their Priorities
134
Interrupt Control Registers
135
Table 3.3 Interrupt Control Registers
135
External Interrupts
145
Figure 3.2 Block Diagram of Interrupt Controller
146
Internal Interrupts
146
Interrupt Operations
146
Figure 3.3 Flow up to Interrupt Acceptance
148
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
149
Figure 3.5 Interrupt Sequence
150
Interrupt Response Time
151
Table 3.4 Interrupt Wait States
151
Section 3 Exception Handling
134
Application Notes
152
Notes on Stack Area Use
152
Figure 3.6 Operation When Odd Address Is Set in SP
152
Notes on Rewriting Port Mode Registers
153
Table 3.5 Conditions under Which Interrupt Request Flag Is Set to 1
154
Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
155
Method for Clearing Interrupt Request Flags
156
Section 4 Clock Pulse Generators
157
Section 4 Clock Pulse Generators
157
Overview
157
Block Diagram
157
System Clock and Subclock
157
Figure 4.1 Block Diagram of Clock Pulse Generators
157
System Clock Generator
158
Figure 4.2 Typical Connection to Crystal Oscillator
158
Figure 4.3 Typical Connection to Ceramic Oscillator
158
Figure 4.4 Board Design of Oscillator Circuit
159
Figure 4.5 External Clock Input (Example)
159
Subclock Generator
160
Figure 4.6 Typical Connection to 32.768 Khz/38.4 Khz Crystal Oscillator (Subclock)
160
Figure 4.7 Equivalent Circuit of 32.768 Khz/38.4 Khz Crystal Oscillator
160
Figure 4.8 Pin Connection When Not Using Subclock
161
Figure 4.9 (A) Pin Connection When Inputting External Clock (H8/38347R Group and H8/3847S Group)
161
Figure 4.9 (B) Pin Connection When Inputting External Clock (H8/38347 Group and H8/38447 Group)
162
Prescalers
163
Note on Oscillators
164
Figure 4.10 Example of Crystal and Ceramic Oscillator Element Arrangement
164
Definition of Oscillation Stabilization Wait Time
165
Figure 4.11 Negative Resistance Measurement and Circuit Modification Suggestions
165
Figure 4.12 Oscillation Stabilization Wait Time
166
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
167
Section 5 Power-Down Modes
169
Overview
169
Table 5.1 Operating Modes
169
Figure 5.1 Mode Transition Diagram
170
Table 5.2 Internal State in each Operating Mode
171
System Control Registers
172
Table 5.3 System Control Registers
172
Section 5 Power-Down Modes
169
Section 5 Power-Down Modes
170
Sleep Mode
176
Transition to Sleep Mode
176
Clearing Sleep Mode
177
Clock Frequency in Sleep (Medium-Speed) Mode
177
Standby Mode
178
Transition to Standby Mode
178
Clearing Standby Mode
178
Oscillator Settling Time after Standby Mode Is Cleared
178
Standby Mode Transition and Pin States
179
Figure 5.2 Standby Mode Transition and Pin States
179
Table 5.4 Clock Frequency and Settling Time (Times Are in Ms)
179
Notes on External Input Signal Changes Before/After Standby Mode
180
Figure 5.3 External Input Signal Capture When Signal Changes Before/After
181
Watch Mode
182
Transition to Watch Mode
182
Clearing Watch Mode
182
Oscillator Settling Time after Watch Mode Is Cleared
182
Notes on External Input Signal Changes Before/After Watch Mode
182
Subsleep Mode
183
Transition to Subsleep Mode
183
Clearing Subsleep Mode
183
Subactive Mode
184
Transition to Subactive Mode
184
Clearing Subactive Mode
184
Operating Frequency in Subactive Mode
184
Active (Medium-Speed) Mode
185
Transition to Active (Medium-Speed) Mode
185
Clearing Active (Medium-Speed) Mode
185
Operating Frequency in Active (Medium-Speed) Mode
185
Direct Transfer
186
Overview of Direct Transfer
186
Direct Transition Times
187
Notes on External Input Signal Changes Before/After Direct Transition
189
Module Standby Mode
190
Setting Module Standby Mode
190
Clearing Module Standby Mode
190
Table 5.5 Setting and Clearing Module Standby Mode by Clock Stop Register
191
Usage Note
192
Section 6 ROM
193
Overview
193
Block Diagram
194
Figure 6.1 ROM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444)
194
Section 6 ROM
194
Section 6 ROM
195
PROM Mode (H8/3847R)
195
Setting to PROM Mode
195
Socket Adapter Pin Arrangement and Memory Map
195
Table 6.1 Setting to PROM Mode
195
Table 6.2 Socket Adapter
195
Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101)
196
Figure 6.3 H8/3847R Memory Map in PROM Mode
197
Programming (H8/3847R)
198
Writing and Verifying
198
Table 6.3 Mode Selection in PROM Mode (H8/3847R)
198
Figure 6.4 High-Speed, High-Reliability Programming Flow Chart
199
Table 6.4 DC Characteristics
200
Table 6.5 AC Characteristics
201
Figure 6.5 PROM Write/Verify Timing
202
Programming Precautions
203
Reliability of Programmed Data
204
Figure 6.6 Recommended Screening Procedure
204
Flash Memory Overview
205
Features
205
Block Diagram
206
Block Configuration
206
Figure 6.7 Block Diagram of Flash Memory
206
Figure 6.8 Flash Memory Block Configuration
207
Register Configuration
208
Table 6.6 Register Configuration
208
Descriptions of Registers of the Flash Memory
209
Flash Memory Control Register 1 (FLMCR1)
209
Flash Memory Control Register 2 (FLMCR2)
212
Erase Block Register (EBR)
212
Flash Memory Power Control Register (FLPWCR)
213
Table 6.7 Division of Blocks to be Erased
213
Flash Memory Enable Register (FENR)
214
On-Board Programming Modes
215
Table 6.8 Setting Programming Modes
215
Boot Mode
216
Table 6.10 Oscillating Frequencies
217
Table 6.9 Boot Mode Operation
217
Programming/Erasing in User Program Mode
218
Flash Memory Programming/Erasing
218
Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode
218
Program/Program-Verify
219
Figure 6.10 Program/Program-Verify Flowchart
220
Table 6.11 Reprogram Data Computation Table
221
Table 6.12 Additional-Program Data Computation Table
221
Table 6.13 Programming Time
221
Erase/Erase-Verify
222
Interrupt Handling When Programming/Erasing Flash Memory
222
Figure 6.11 Erase/Erase-Verify Flowchart
223
Program/Erase Protection
224
Hardware Protection
224
Software Protection
224
Error Protection
224
Programmer Mode
225
Socket Adapter
225
Programmer Mode Commands
225
Table 6.14 Command Sequence in Programmer Mode
226
Figure 6.12 Socket Adapter Pin Correspondence Diagram
227
Memory Read Mode
228
Table 6.15 AC Characteristics in Transition to Memory Read Mode
228
Figure 6.13 Timing Waveforms for Memory Read after Memory Write
229
Table 6.16 AC Characteristics in Transition from Memory Read Mode to Another Mode
229
Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode
230
Figure 6.15 CE and OE Enable State Read Timing Waveforms
230
Table 6.17 AC Characteristics in Memory Read Mode
230
Auto-Program Mode
231
Figure 6.16 CE and OE Clock System Read Timing Waveforms
231
Figure 6.17 Auto-Program Mode Timing Waveforms
232
Table 6.18 AC Characteristics in Auto-Program Mode
232
Auto-Erase Mode
233
Table 6.19 AC Characteristics in Auto-Erase Mode
233
Status Read Mode
234
Figure 6.18 Auto-Erase Mode Timing Waveforms
234
Figure 6.19 Status Read Mode Timing Waveforms
235
Table 6.20 AC Characteristics in Status Read Mode
235
Status Polling
236
Table 6.21 Status Read Mode Return Codes
236
Table 6.22 Status Polling Output Truth Table
236
Programmer Mode Transition Time
237
Notes on Memory Programming
237
Figure 6.20 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence
237
Table 6.23 Stipulated Transition Times to Command Wait State
237
Power-Down States for Flash Memory
238
Table 6.24 Flash Memory Operating States
238
Section 7 RAM
239
Section 7 RAM
239
Overview
239
Block Diagram
239
Figure 7.1 RAM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444)
239
Section 8 I/O Ports
241
Section 8 I/O Ports
241
Overview
241
Table 8.1 Port Functions
241
Section 8 I/O Ports
243
Port 1
243
Overview
243
Register Configuration and Description
243
Figure 8.1 Port 1 Pin Configuration
243
Table 8.2 Port 1 Registers
243
Pin Functions
248
Table 8.3 Port 1 Pin Functions
248
Pin States
249
Table 8.4 Port 1 Pin States
249
MOS Input Pull-Up
250
Port 2
251
Overview
251
Register Configuration and Description
251
Figure 8.2 Port 2 Pin Configuration
251
Table 8.5 Port 2 Registers
251
Pin Function
255
Table 8.6 Port 2 Pin Functions
255
Pin States
256
Table 8.7 Port 2 Pin States
256
Port 3
257
Overview
257
Register Configuration and Description
257
Figure 8.3 Port 3 Pin Configuration
257
Table 8.8 Port 3 Registers
257
Pin Functions
261
Table 8.9 Port 3 Pin Functions
261
Pin States
263
MOS Input Pull-Up
263
Table 8.10 Port 3 Pin States
263
Port 4
264
Overview
264
Register Configuration and Description
264
Figure 8.4 Port 4 Pin Configuration
264
Table 8.11 Port 4 Registers
264
Pin Functions
266
Table 8.12 Port 4 Pin Functions
266
Pin States
267
Table 8.13 Port 4 Pin States
267
Port 5
268
Overview
268
Register Configuration and Description
268
Figure 8.5 Port 5 Pin Configuration
268
Table 8.14 Port 5 Registers
268
Pin Functions
270
Table 8.15 Port 5 Pin Functions
270
Pin States
271
MOS Input Pull-Up
271
Table 8.16 Port 5 Pin States
271
Port 6
272
Overview
272
Register Configuration and Description
272
Figure 8.6 Port 6 Pin Configuration
272
Table 8.17 Port 6 Registers
272
Pin Functions
274
Table 8.18 Port 6 Pin Functions
274
Table 8.19 Port 6 Pin States
274
MOS Input Pull-Up
275
Overview
276
Register Configuration and Description
276
Figure 8.7 Port 7 Pin Configuration
276
Table 8.20 Port 7 Registers
276
Pin Functions
278
Pin States
278
Table 8.21 Port 7 Pin Functions
278
Table 8.22 Port 7 Pin States
278
Overview
279
Register Configuration and Description
279
Figure 8.8 Port 8 Pin Configuration
279
Table 8.23 Port 8 Registers
279
Pin Functions
281
Pin States
281
Table 8.24 Port 8 Pin Functions
281
Table 8.25 Port 8 Pin States
281
8.8 Port 7
276
8.9 Port 8
279
Port 9
282
Overview
282
Register Configuration and Description
282
Figure 8.9 Port 9 Pin Configuration
282
Table 8.26 Port 9 Registers
282
Pin Functions
284
Table 8.27 Port 9 Pin Functions
284
Pin States
285
Table 8.28 Port 9 Pin States
285
Port a
286
Overview
286
Register Configuration and Description
286
Figure 8.10 Port a Pin Configuration
286
Table 8.29 Port a Registers
286
Pin Functions
288
Pin States
288
Table 8.30 Port a Pin Functions
288
Table 8.31 Port a Pin States
288
Port B
289
Overview
289
Register Configuration and Description
289
Figure 8.11 Port B Pin Configuration
289
Table 8.32 Port B Register
289
Port C
290
Overview
290
Register Configuration and Description
290
Figure 8.12 Port C Pin Configuration
290
Table 8.33 Port C Register
290
Input/Output Data Inversion Function
291
Overview
291
Register Configuration and Descriptions
291
Figure 8.13 Input/Output Data Inversion Function
291
Table 8.34 Register Configuration
291
Note on Modification of Serial Port Control Register
294
Application Note
294
The Management of the Un-Use Terminal
294
Section 9 Timers
295
Section 9 Timers
295
Overview
295
Table 9.1 Timer Functions
295
Timer a
296
Overview
296
Figure 9.1 Block Diagram of Timer a
297
Table 9.2 Pin Configuration
297
Register Descriptions
298
Table 9.3 Timer a Registers
298
Timer Operation
302
Timer a Operation States
303
Application Note
303
Table 9.4 Timer a Operation States
303
Section 9 Timers
297
Timer C
304
Overview
304
Figure 9.2 Block Diagram of Timer C
305
Table 9.5 Pin Configuration
305
Register Descriptions
306
Table 9.6 Timer C Registers
306
Timer Operation
309
Timer C Operation States
311
Table 9.7 Timer C Operation States
311
Usage Note
312
Timer F
313
Overview
313
Figure 9.3 Block Diagram of Timer F
314
Table 9.8 Pin Configuration
315
Table 9.9 Timer F Registers
315
Register Descriptions
316
CPU Interface
323
Figure 9.4 Write Access to TCR (CPU → TCF)
324
Figure 9.5 Read Access to TCF (TCF → CPU)
325
Operation
326
Figure 9.6 TMOFH/TMOFL Output Timing
327
Table 9.10 Timer F Operation Modes
328
Application Notes
329
Figure 9.7 Clear Interrupt Request Flag When Interrupt Factor Generation Signal
331
Timer G
332
Overview
332
Figure 9.8 Block Diagram of Timer G
333
Register Descriptions
334
Table 9.11 Pin Configuration
334
Table 9.12 Timer G Registers
334
Noise Canceler
339
Figure 9.9 Noise Canceler Block Diagram
339
Operation
340
Figure 9.10 Noise Canceler Timing (Example)
340
Figure 9.11 Input Capture Input Timing (Without Noise Cancellation Function)
342
Figure 9.12 Input Capture Input Timing (with Noise Cancellation Function)
342
Figure 9.13 Timing of Input Capture by Input Capture Input
343
Figure 9.14 TCG Clear Timing
343
Application Notes
344
Table 9.13 Timer G Operation Modes
344
Table 9.14 Internal Clock Switching and TCG Operation
345
Table 9.15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching
347
Table 9.16 Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching, and Conditions for Their Occurrence
347
Figure 9.15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing Procedure
348
Timer G Application Example
349
Figure 9.16 Timer G Application Example
349
Watchdog Timer
350
Overview
350
Figure 9.17 Block Diagram of Watchdog Timer
350
Register Descriptions
351
Table 9.17 Watchdog Timer Registers
351
Timer Operation
355
Figure 9.18 Typical Watchdog Timer Operations (Example)
356
Watchdog Timer Operation States
357
Table 9.18 Watchdog Timer Operation States
357
Asynchronous Event Counter (AEC)
358
Overview
358
Figure 9.19 Block Diagram of Asynchronous Event Counter
359
Table 9.19 Pin Configuration
359
Register Descriptions
360
Table 9.20 Asynchronous Event Counter Registers
360
Operation
365
Figure 9.20 Example of Software Processing When Using ECH and ECL as 16-Bit Event Counter
365
Figure 9.21 Example of Software Processing When Using ECH and ECL as 8-Bit Event Counters
366
Asynchronous Event Counter Operation Modes
367
Application Notes
367
Table 9.21 Asynchronous Event Counter Operation Modes
367
Section 10 Serial Communication Interface
369
Section 10 Serial Communication Interface
369
Overview
369
Table 10.1 Overview of SCI Functions
369
Sci1
370
Overview
370
Figure 10.1 SCI1 Block Diagram
371
Register Descriptions
372
Table 10.2 SCI1 Pin Configuration
372
Table 10.3 Registers
372
Operation
378
Figure 10.2 Transfer Format
378
Operation in SSB Mode
381
Figure 10.3 Example of SSB Connections
381
Figure 10.4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1)
382
Figure 10.5 HOLD TAIL and LATCH TAIL Output Waveforms
382
Interrupt Source
384
Application Notes
384
Section 10 Serial Communication Interface
371
Sci3
385
Overview
385
Figure 10.6 SCI3 Block Diagram
387
Table 10.4 Pin Configuration
388
Table 10.5 Registers
388
Register Descriptions
389
Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
403
Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
404
Table 10.7 Relation between N and Clock
404
Table 10.8 Maximum Bit Rate for each Frequency (Asynchronous Mode)
405
Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1)
406
Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2)
407
Table 10.10 Relation between N and Clock
408
Operation
412
Table 10.11 SMR Settings and Corresponding Data Transfer Formats
413
Table 10.12 SMR and SCR3 Settings and Clock Source Selection
414
Table 10.13 Transmit/Receive Interrupts
415
Figure 10.7 (A) RDRF Setting and RXI Interrupt
416
Figure 10.7 (B) TDRE Setting and TXI Interrupt
416
Figure 10.7 (C) TEND Setting and TEI Interrupt
416
Figure 10.8 Data Format in Asynchronous Communication
417
Table 10.14 Data Transfer Formats (Asynchronous Mode)
418
Figure 10.9 Phase Relationship between Output Clock and Transfer Data (Asynchronous Mode) (8-Bit Data, Parity, 2 Stop Bits)
419
Figure 10.10 Example of SCI3 Initialization Flowchart
420
Figure 10.11 Example of Data Transmission Flowchart (Asynchronous Mode)
421
Figure 10.12 Example of Operation When Transmitting in Asynchronous Mode (8-Bit Data, Parity, 1 Stop Bit)
422
Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode)
423
Table 10.15 Receive Error Detection Conditions and Receive Data Processing
425
Figure 10.14 Example of Operation When Receiving in Asynchronous Mode (8-Bit Data, Parity, 1 Stop Bit)
426
Figure 10.15 Data Format in Synchronous Communication
427
Figure 10.16 Example of Data Transmission Flowchart (Synchronous Mode)
429
Figure 10.17 Example of Operation When Transmitting in Synchronous Mode
430
Figure 10.18 Example of Data Reception Flowchart (Synchronous Mode)
431
Figure 10.19 Example of Operation When Receiving in Synchronous Mode
432
Figure 10.20 Example of Simultaneous Data Transmission/Reception Flowchart (Synchronous Mode)
433
Figure 10.21 Example of Inter-Processor Communication Using Multiprocessor Format (Sending Data H'AA to Receiver A)
435
Figure 10.22 Example of Multiprocessor Data Transmission Flowchart
436
Figure 10.23 Example of Operation When Transmitting Using Multiprocessor Format (8-Bit Data, Multiprocessor Bit, 1 Stop Bit)
437
Figure 10.24 Example of Multiprocessor Data Reception Flowchart
438
Figure 10.25 Example of Operation When Receiving Using Multiprocessor Format (8-Bit Data, Multiprocessor Bit, 1 Stop Bit)
440
Interrupts
441
Table 10.16 SCI3 Interrupt Requests
441
Application Notes
442
Table 10.17 SSR Status Flag States and Receive Data Transfer
442
Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode
444
Figure 10.27 Relation between RDR Read Timing and Data
445
Section 11 14-Bit PWM
447
Overview
447
Features
447
Section 11 14-Bit PWM
448
Block Diagram
448
Pin Configuration
448
Figure 11.1 Block Diagram of the 14 Bit PWM
448
Table 11.1 Pin Configuration
448
Register Configuration
449
Section 11 14-Bit PWM
448
Register Descriptions
449
PWM Control Register (PWCR)
449
Table 11.2 Register Configuration
449
PWM Data Registers U and L (PWDRU, PWDRL)
451
Clock Stop Register 2 (CKSTPR2)
452
Operation
453
PWM Operation Modes
454
Figure 11.2 PWM Output Waveform
454
Table 11.3 PWM Operation Modes
454
Section 12 A/D Converter
455
Overview
455
Features
455
Block Diagram
456
Figure 12.1 Block Diagram of the A/D Converter
456
Pin Configuration
457
Register Configuration
457
Table 12.1 Pin Configuration
457
Table 12.2 Register Configuration
457
Section 12 A/D Converter
456
Section 12 A/D Converter
457
Register Descriptions
458
A/D Result Registers (ADRRH, ADRRL)
458
A/D Mode Register (AMR)
458
A/D Start Register (ADSR)
460
Clock Stop Register 1 (CKSTPR1)
461
Operation
462
A/D Conversion Operation
462
Start of A/D Conversion by External Trigger Input
462
Figure 12.2 External Trigger Input Timing
462
A/D Converter Operation Modes
463
Interrupts
463
Typical Use
463
Table 12.3 A/D Converter Operation Modes
463
Figure 12.3 Typical A/D Converter Operation Timing
464
Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
465
Application Notes
466
Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)
466
Figure 12.6 Analog Input Circuit Example
467
Influences on Absolute Precision
467
Permissible Signal Source Impedance
467
Section 13 LCD Controller/Driver
469
Overview
469
Features
469
Block Diagram
470
Figure 13.1 Block Diagram of LCD Controller/Driver
470
Pin Configuration
471
Register Configuration
471
Table 13.1 Pin Configuration
471
Table 13.2 LCD Controller/Driver Registers
471
Section 13 LCD Controller/Driver
470
Section 13 LCD Controller/Driver
471
Register Descriptions
472
LCD Port Control Register (LPCR)
472
LCD Control Register (LCR)
474
LCD Control Register 2 (LCR2)
476
Figure 13.2 Example of a Waveform with 1/2 Duty and 1/2 Bias
477
Clock Stop Register 2 (CKSTPR2)
478
Operation
479
Settings up to LCD Display
479
Luminance Adjustment Function
479
Figure 13.3 Handling of LCD Drive Power Supply When Using 1/2 Duty
479
Figure 13.4 Examples of LCD Power Supply Pin Connections
480
Relationship between LCD RAM and Display
482
Figure 13.5 LCD RAM Map with Segments Not Externally Expanded (1/4 Duty)
482
Figure 13.6 LCD RAM Map with Segments Not Externally Expanded (1/3 Duty)
483
Figure 13.7 LCD RAM Map with Segments Not Externally Expanded (1/2 Duty)
484
Figure 13.8 LCD RAM Map with Segments Not Externally Expanded (Static Mode)
485
Figure 13.9 LCD RAM Map with Segment Externally Expanded (SGX = "1", SGS3 to SGS0 = "0000" 1/4 Duty)
486
Figure 13.10 LCD RAM Map with Segment Externally Expanded (SGX = "1", SGS3 to SGS0 = "0000" 1/3 Duty)
487
Figure 13.11 LCD RAM Map with Segment Externally Expanded (SGX = "1", SGS3 to SGS0 = "0000" 1/2 Duty)
488
Figure 13.12 LCD RAM Map with Segment Externally Expanded (SGX = "1", SGS3 to SGS0 = "0000" Static)
489
Pin)
490
Figure 13.13 LCD Drive Power Supply Unit
490
Low-Power-Consumption LCD Drive System
491
Figure 13.14 Example of Low-Power-Consumption LCD Drive Operation
492
Figure 13.15 Output Waveforms for each Duty Cycle (a Waveform)
493
Figure 13.16 Output Waveforms for each Duty Cycle (B Waveform)
494
Operation in Power-Down Modes
495
Table 13.3 Output Levels
495
Table 13.4 Power-Down Modes and Display Operation
495
Boosting the LCD Drive Power Supply
496
Figure 13.17 Connection of External Split-Resistance
496
Connection to HD66100
497
Figure 13.18 Connection to HD66100
498
Section 14 Power Supply Circuit
499
Section 14 Power Supply Circuit
499
Overview
499
When Using Internal Power Supply Step-Down Circuit
499
Figure 14.1 Power Supply Connection When Internal Step-Down Circuit Is Used
499
When Not Using Internal Power Supply Step-Down Circuit
500
H8/3847S Group
500
Notes on Switching from the H8/3847R to the H8/38347 or H8/38447
500
Figure 14.2 Power Supply Connection When Internal Step-Down Circuit Is Not Used
500
Section 15 Electrical Characteristics
501
Section 15 Electrical Characteristics
501
H8/3847R Group Absolute Maximum Ratings (Regular Specifications)
501
Table 15.1 Absolute Maximum Ratings
501
H8/3847R Electrical Characteristics (Regular Specifications)
502
Power Supply Voltage and Operating Range
502
DC Characteristics
505
Table 15.2 DC Characteristics
505
AC Characteristics
510
Table 15.3 Control Signal Timing
510
Table 15.4 Serial Interface (SCI1) Timing
513
Table 15.5 Serial Interface (SCI3-1, SCI3-2) Timing
514
A/D Converter Characteristics
515
Table 15.6 A/D Converter Characteristics
515
LCD Characteristics
516
Table 15.7 LCD Characteristics
516
Table 15.8 Segment External Expansion AC Characteristics
517
H8/3847R Group Absolute Maximum Ratings (Wide-Range Specification)
518
Table 15.9 Absolute Maximum Ratings
518
H8/3847R Electrical Characteristics (Wide-Range Specification)
519
Power Supply Voltage and Operating Range
519
DC Characteristics
522
Table 15.10 DC Characteristics
522
AC Characteristics
527
Table 15.11 Control Signal Timing
527
Table 15.12 Serial Interface (SCI1) Timing
530
Table 15.13 Serial Interface (SCI3-1, SCI3-2) Timing
531
A/D Converter Characteristics
532
Table 15.14 A/D Converter Characteristics
532
LCD Characteristics
533
Table 15.15 LCD Characteristics
533
Table 15.16 Segment External Expansion AC Characteristics
534
H8/3847S Group Absolute Maximum Ratings
535
Table 15.17 Absolute Maximum Ratings
535
H8/3847S Group Electrical Characteristics
536
Power Supply Voltage and Operating Range
536
DC Characteristics
538
Table 15.18 DC Characteristics
538
AC Characteristics
543
Table 15.19 Control Signal Timing
543
Table 15.20 Serial Interface (SCI1) Timing
546
Table 15.21 Serial Interface (SCI3-1, SCI3-2) Timing
547
A/D Converter Characteristics
548
Table 15.22 A/D Converter Characteristics
548
LCD Characteristics
549
Table 15.23 LCD Characteristics
549
Table 15.24 Segment External Expansion AC Characteristics
550
Absolute Maximum Ratings of H8/38347 Group and H8/38447 Group
551
Table 15.25 Absolute Maximum Ratings
551
Electrical Characteristics of H8/38347 Group and H8/38447 Group
552
Power Supply Voltage and Operating Ranges
552
DC Characteristics
555
Table 15.26 DC Characteristics
555
AC Characteristics
564
Table 15.27 Control Signal Timing
564
Table 15.28 Serial Interface (SCI1) Timing
566
Table 15.29 Serial Interface (SCI3) Timing
567
A/D Converter Characteristics
568
Table 15.30 A/D Converter Characteristics
568
LCD Characteristics
569
Table 15.31 LCD Characteristics
569
Flash Memory Characteristics
570
Table 15.32 Flash Memory Characteristics
570
Section 15 Electrical Characteristics
573
Operation Timing
573
Figure 15.1 Clock Input Timing
573
Figure 15.2 RES Low Width
573
Figure 15.3 Input Timing
573
Figure 15.4 UD Pin Minimum Modulation Width Timing
574
Figure 15.5 SCI1 Input/Output Timing
574
Figure 15.6 SCK3 Input Clock Timing
575
Figure 15.7 SCI3 Synchronous Mode Input/Output Timing
575
Figure 15.8 Segment Expansion Signal Timing
576
Output Load Circuit
577
Figure 15.9 Output Load Condition
577
Resonator
578
Figure 15.10 Resonator Equivalent Circuit
578
Figure 15.11 Recommended Resonators
578
Usage Note
579
Appendix A CPU Instruction Set
581
Instructions
581
Operation Code Map
589
Number of Execution States
591
Appendix B Internal I/O Registers
598
Addresses
598
Functions
602
Appendix C I/O Port Block Diagrams
668
Block Diagrams of Port 1
668
Figure C.1 (A) Port 1 Block Diagram (Pins P1
668
To P1
668
Figure C.1 (B) Port 1 Block Diagram (Pin P1
669
Figure C.1 (C) Port 1 Block Diagram (Pin P1
670
Figure C.1 (D) Port 1 Block Diagram (Pin P1
671
Block Diagrams of Port 2
672
Figure C.2 (A-1) Port 2 Block Diagram (Pins P2
672
Of the H8/38347 Group and H8/38447 Group)
672
To P2 3 , Not Including P2
672
And H8/38447 Group)
673
Figure C.2 (A-2) Port 2 Block Diagram (Pin P2
673
Figure C.2 (B) Port 2 Block Diagram (Pin P2
674
Figure C.2 (C) Port 2 Block Diagram (Pin P2
675
Figure C.2 (D) Port 2 Block Diagram (Pin P2
676
Figure C.3 (A) Port 3 Block Diagram (Pin P3
677
To P3
677
Figure C.3 (B) Port 3 Block Diagram (Pin P3
678
Figure C.3 (C) Port 3 Block Diagram (Pin P3
679
Figure C.3 (D) Port 3 Block Diagram (Pin P3
680
Figure C.3 (E-1) Port 3 Block Diagram (Pin P3
681
H8/3847R Group and H8/3847S Group)
681
Figure C.3 (E-2) Port 3 Block Diagram (Pin P3
682
H8/38347 Group and H8/38447 Group)
682
Figure C.3 (F-1) Port 3 Block Diagram (Pin P3
683
H8/3847R Group and H8/3847S Group))
683
Figure C.3 (F-2) Port 3 Block Diagram (Pin P3
684
H8/38347 Group and H8/38447 Group)
684
Figure C.3 (G) Port 3 Block Diagram (Pin P3
685
Figure C.4 (A) Port 4 Block Diagram (Pin P4
686
Figure C.4 (B) Port 4 Block Diagram (Pin P4
687
Figure C.4 (C) Port 4 Block Diagram (Pin P4
688
Figure C.4 (D) Port 4 Block Diagram (Pin P4
689
Figure C.5 Port 5 Block Diagram
690
Figure C.6 Port 6 Block Diagram
691
Figure C.7 Port 7 Block Diagram
692
Figure C.8 Port 8 Block Diagram
693
Figure C.9 Port 9 Block Diagram
694
Figure F.1 FP-100A Package Dimensions
706
Figure F.2 FP-100B Package Dimensions
707
Figure F.3 TFP-100B Package Dimensions
708
Figure F.4 TFP-100G Package Dimensions
709
Figure G.1 Chip Sectional Figure
710
Figure G.2 Chip Sectional Figure
710
Figure G.3 Chip Sectional Figure
711
Figure G.4 Chip Sectional Figure
711
Figure H.1 Bonding Pad Form
712
Figure H.2 Bonding Pad Form
713
Figure H.3 Bonding Pad Form
714
Figure C.10 Port a Block Diagram
695
Figure C.11 Port B Block Diagram
696
Figure C.12 Port C Block Diagram
697
Appendix F Package Dimensions
706
Appendix G Specifications of Chip Form
710
Appendix H Form of Bonding Pads
712
Appendix I Specifications of Chip Tray
715
Figure I.1 Specifications of Chip Tray
715
Figure I.2 Specifications of Chip Tray
716
Figure I.3 Specifications of Chip Tray
717
Figure I.4 Specifications of Chip Tray
718
Advertisement
Advertisement
Related Products
Renesas H8/38447 Series
Renesas H8/3844R
Renesas H8/38442
Renesas H8/38443
Renesas H8/38444
Renesas H8/38445
Renesas H8/38446
Renesas H8/3847R Series
Renesas H8/3847S Series
Renesas H8/3843R
Renesas Categories
Computer Hardware
Motherboard
Microcontrollers
Adapter
Switch
More Renesas Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL