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Appendix B Internal I/O Registers
PWCR—PWM Control Register
Bit
7
Initial value
1
Read/Write
Clock select
0 The input clock is φ/2 (tφ* = 2/φ)
The conversion period is 16,384/φ, with a minimum modulation width of 1/φ
The input clock is φ/4 (tφ* = 4/φ)
The conversion period is 32,768/φ, with a minimum modulation width of 2/φ
1 The input clock is φ/8 (tφ* = 8/φ)
The conversion period is 65,536/φ, with a minimum modulation width of 4/φ
The input clock is φ/16 (tφ* = 16/φ)
The conversion period is 131,072/φ, with a minimum modulation width of 8/φ
Note: tφ: Period of PWM input clock
*
PWDRU—PWM Data Register U
Bit
7
—
Initial value
1
Read/Write
—
PWDRL—PWM Data Register L
Bit
7
PWDRL7
Initial value
0
Read/Write
W
Rev. 6.00 Aug 04, 2006 page 610 of 680
REJ09B0145-0600
6
5
1
1
6
5
—
PWDRU5 PWDRU4 PWDRU3
1
0
—
W
Upper 6 bits of data for generating PWM waveform
6
5
PWDRL6
PWDRL5 PWDRL4 PWDRL3
0
0
W
W
Lower 8 bits of data for generating PWM waveform
H'D0
4
3
2
1
1
1
H'D1
4
3
2
PWDRU2 PWDUR1
0
0
0
W
W
W
H'D2
4
3
2
PWDRL2 PWDRL1
0
0
0
W
W
W
14-bit PWM
1
0
PWCR1
PWCR0
0
0
W
W
14-bit PWM
1
0
PWDRU0
0
0
W
W
14-bit PWM
1
0
PWDRL0
0
0
W
W
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