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Section 10 Serial Communication Interface
Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φ/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate
register (BRR).
Bit 1
Bit 0
CKS1
CKS0
0
0
0
1
1
0
1
1
Notes: 1. φ
/2 clock is selected in active (medium- and high-speed) or sleep (medium- and high-
W
speed) mode.
2. φ
clock is selected in subactive or subsleep mode. SCI3 can be used only when the
W
φ
/2 is selected as the CPU clock in subactive or subsleep mode.
W
6. Serial Control Register 3 (SCR3)
Bit
7
TIE
Initial value
0
Read/Write
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, watch or module standby mode.
Rev. 6.00 Aug 04, 2006 page 356 of 680
REJ09B0145-0600
Description
φ clock
/2 clock *
1
clock *
φ
/φ
W
W
φ/16 clock
φ/64 clock
6
5
RIE
TE
0
0
R/W
R/W
2
4
3
RE
MPIE
0
0
R/W
R/W
(initial value)
2
1
TEIE
CKE1
CKE0
0
0
R/W
R/W
R/W
0
0
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