Renesas H8/3847R Series Hardware Manual page 142

Section 3 Exception Handling
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT Description
0 Clearing condition:
When IRRDT = 1, it is cleared by writing 0
1 Setting condition:
When a direct transfer is made by executing a SLEEP instruction
while DTON = 1 in SYSCR2
Bit 6: A/D converter interrupt request flag (IRRAD)
Bit 6
IRRAD Description
0 Clearing condition:
When IRRAD = 1, it is cleared by writing 0
1 Setting condition:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4: Timer G interrupt request flag (IRRTG)
Bit 4
IRRTG Description
0 Clearing condition:
When IRRTG = 1, it is cleared by writing 0
1 Setting condition:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Rev. 6.00 Aug 04, 2006 page 104 of 680
REJ09B0145-0600
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