Renesas H8/3847R Series Hardware Manual page 475

8-bit single-chip microcomputer super low power

Table of Contents

Bit 4: Display data control (DISP)

Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless

of the LCD RAM contents.

Blank data is displayed

LCD RAM data is display

Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0)

Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,

and subsleep mode, the system clock (φ) is halted, and therefore display operations are not

performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these

modes, φw, φw/2, or φw/4 must be selected as the operating clock.

Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz.

2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.

3. This is the frame frequency when φw = 32.768 kHz.

Operating Clock

Section 13 LCD Controller/Driver

Frame Frequency *

φ φ φ φ = 2 MHz

(initial value)

Rev. 6.00 Aug 04, 2006 page 437 of 680

(initial value)

φ φ φ φ = 250 kHz *

*: Don't care

REJ09B0145-0600