Renesas H8/3847R Series Hardware Manual page 174

Section 5 Power-Down Modes
Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0)
Bits 1 and 0 choose φ
(medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in
active (high-speed) mode or subactive mode.
Bit 1 Bit 0
MA1 MA0
0 0
0 1
1 0
1 1
2. System Control Register 2 (SYSCR2)
Bit 7
—
Initial value 1
Read/Write —
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (φ
pulse generator is sampled, in relation to the oscillator clock (φ
pulse generator. When φ
Bit 4
NESEL Description
Sampling rate is φ
0
Sampling rate is φ
1
Rev. 6.00 Aug 04, 2006 page 136 of 680
REJ09B0145-0600
/128, φ /64, φ
OSC OSC OSC
Description
φ
/16
OSC
φ
/32
OSC
φ
/64
OSC
φ
/128
OSC
6 5
— —
1 1
— —
= 2 to 16 MHz, clear NESEL to 0.
OSC
/16
OSC
/4
OSC
/32, or φ
/16 as the operating clock in active
OSC
4 3
NESEL DTON
1 0
R/W R/W
W
OSC
(initial value)
2 1
MSON SA1
0 0
R/W R/W
) generated by the subclock
) generated by the system clock
(initial value)
0
SA0
0
R/W