Renesas H8/3847R Series Hardware Manual page 353

8-bit single-chip microcomputer super low power

Table of Contents

Bit 2: Watchdog timer on (WDON)

Bit 2 enables watchdog timer operation.

Watchdog timer operation is disabled

Clearing condition:

Reset, or when TCSRWE = 1 and 0 is written in both B2WI and

Watchdog timer operation is enabled

Setting condition:

When TCSRWE = 1 and 0 is written in B2WI and 1 is written in

Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.

Bit 1: Bit 0 write inhibit (B0WI)

Bit 1 controls the writing of data to bit 0 in TCSRW.

Bit 0 is write-enabled

Bit 0 is write-protected

This bit is always read as 1. Data written to this bit is not stored.

Bit 0: Watchdog timer reset (WRST)

Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset

signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the

RES pin, or when software writes 0.

Clearing condition:

Reset by RES pin

When TCSRWE = 1, and 0 is written in both B0WI and WRST

Setting condition:

When TCW overflows and an internal reset signal is generated

Rev. 6.00 Aug 04, 2006 page 315 of 680

Section 9 Timers

(initial value)

REJ09B0145-0600