Renesas H8/3847R Series Hardware Manual page 125

[C: After executing BSET]
P3
7
Input/output Input
Pin state Low
level
PCR3 0
PDR3 0
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P3 and P3 are input pins, the CPU reads the pin states (low-level and high-level input).
7 6
P3 to P3 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
5 0
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P3
However, bits 7 and 6 of PDR3 end up with different values.
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B #H'80 ,
MOV. B R0L ,
MOV. B R0L ,
P3
7
Input/output Input
Pin state Low
level
PCR3 0
PDR3 1
RAM0 1
P3 P3
6 5
Input Output
High Low
level level
0 1
1 0
The PDR3 value (H'80) is written to a work area in
R0L
memory (RAM0) as well as to PDR3.
@RAM0
@PDR3
P3 P3
6 5
Input Output
High Low
level level
0 1
0 0
0 0
P3 P3 P3
4 3
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
outputs a high-level signal.
0
P3 P3 P3
4 3
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
0 0 0
Rev. 6.00 Aug 04, 2006 page 87 of 680
Section 2 CPU
P3 P3
2 1 0
Output Output
Low High
level level
1 1
0 1
P3 P3
2 1 0
Output Output
Low Low
level level
1 1
0 0
0 0
REJ09B0145-0600