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AMR—A/D Mode Register
Bit
7
CKS
Initial value
0
Read/Write
R/W
Clock select
Bit 7
CKS
6
5
TRGE
0
1
R/W
Channel select
External trigger select
0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge
of external trigger at pin ADTRG
Conversion Period
0
62/φ
1
31/φ
Appendix B Internal I/O Registers
4
3
CH3
1
0
R/W
Bit 3
Bit 2
Bit 1
CH3
CH2
CH1
0
0
*
0
1
0
0
1
0
0
1
1
1
0
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Conversion Time
φ = 1 MHz
φ = 5 MHz
62 µs
12.4 µs
31 µs
Rev. 6.00 Aug 04, 2006 page 603 of 680
H'C6
A/D converter
2
1
CH2
CH1
0
0
R/W
R/W
Bit 0
CH0
Analog Input Channel
No channel selected
*
0
AN
0
1
AN
1
0
AN
2
1
AN
3
0
AN
4
1
AN
5
0
AN
6
1
AN
7
0
AN
8
1
AN
9
0
AN
10
1
AN
11
* Don't care
REJ09B0145-0600
0
CH0
0
R/W
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