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IRR1—Interrupt Request Register 1
Bit
7
IRRTA
Initial value
0
R/(W) *
Read/Write
Timer A interrupt request flag
0 [Clearing condition]
1 [Setting condition]
Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing.
6
5
IRRS1
0
1
R/(W) *
IRQ4 to IRQ0 interrupt request flags
0 [Clearing condition]
1 [Setting condition]
SCI1 interrupt request flag
0 [Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1 [Setting condition]
When SCI1 completes transfer
When IRRTA = 1, it is cleared by writing 0
When the timer A counter value overflows (from H'FF to H'00)
Appendix B Internal I/O Registers
H'F6
4
3
IRRI4
IRRI3
IRRI2
0
0
R/(W) *
R/(W) *
R/(W) *
When IRRIn = 1, it is cleared by writing 0
When pin IRQn is designated for interrupt
input and the designated signal edge is input
Rev. 6.00 Aug 04, 2006 page 625 of 680
System control
2
1
0
IRRI1
IRRI0
0
0
0
R/(W) *
R/(W) *
(n = 4 to 0)
REJ09B0145-0600
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