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SDRU read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRU is undefined upon reset.
4. Serial Data Register L (SDRL)
Bit
7
SDRL7
Initial value
Undefined
Read/Write
R/W
SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits).
In 8-bit transfer, the data written into SDRL is output from the SO
replacement process, data is input LSB-first from the SI
LSB direction.
The operation in 16-bit transfer is the same as for 8-bit transfer, except that the input data is taken
from SDRU.
SDRL read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRL is undefined upon reset.
5. Clock Stop Register 1 (CKSTPR1)
Bit
7
S1CKSTP
Initial value
1
Read/Write
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to SCI1 is described here. For details of the other bits, see the
sections on the relevant modules.
6
5
SDRL6
SDRL5
Undefined
Undefined
R/W
R/W
6
5
S31CKSTP S32CKSTP ADCKSTP TGCKSTP
1
1
R/W
R/W
Section 10 Serial Communication Interface
4
3
SDRL4
SDRL3
SDRL2
Undefined
Undefined
Undefined
R/W
R/W
pin in LSB-first order. In the
1
pin, and the data is shifted in the MSB →
1
4
3
TFCKSTP TCCKSTP TACKSTP
1
1
R/W
R/W
Rev. 6.00 Aug 04, 2006 page 339 of 680
2
1
SDRL1
SDRL0
Undefined
Undefined
R/W
R/W
R/W
2
1
1
1
R/W
R/W
R/W
REJ09B0145-0600
0
0
1
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