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TMG—Timer Mode Register G
Bit
7
OVFH
Initial value
0
Read/Write
R/(W)*
Timer overflow interrupt enable
0
1
Timer overflow flag L
0 [Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1 [Setting condition]
Set when TCG overflows from H'FF to H'00
Timer overflow flag H
0 [Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1 [Setting condition]
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
6
5
OVFL
OVIE
IIEGS
0
0
R/(W)*
W
Counter clear
0
0
TCG clearing is disabled
1
TCG cleared by falling edge of input capture input signal
0
0
TCG cleared by rising edge of input capture input signal
1
1
TCG cleared by both edges of input capture input signal
1
Input capture interrupt edge select
0 Interrupt generated on rising edge of input capture input signal
1 Interrupt generated on falling edge of input capture input signal
TCG overflow interrupt request is disabled
TCG overflow interrupt request is enabled
Appendix B Internal I/O Registers
4
3
2
CCLR1
CCLR0
0
0
0
W
W
W
Clock select
0
0
0
1
1
0
1
1
Rev. 6.00 Aug 04, 2006 page 597 of 680
H'BC
Timer G
1
0
CKS1
CKS0
0
0
W
W
Internal clock: counting on φ /64
Internal clock: counting on φ /32
Internal clock: counting on φ /2
Internal clock: counting on φ w/4
REJ09B0145-0600
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