Note 1: System Bus Address Cycle Failures - DEC 4000 AXP Service Manual

Table 4–2 (Cont.) Error Field Bit Definitions for Error Log Interpretation
Error Field Bits
W1-Byte-1, Memory Correctable Errors
<0> MEM0_CORR
<1> MEM1_CORR
<2> MEM2_CORR
<3> MEM3_CORR
W2-Byte-0, Sync Errors (the two gate arrays are not working together)
<0> MEM0_SYNC_Error
<1> MEM1_SYNC_Error
<2> MEM2_SYNC_Error
<3> MEM3_SYNC_Error

4.4.1 Note 1: System Bus Address Cycle Failures

Synopsis:
System bus address cycle failures can be reported by the bus commander,
responders, or both:
• By commander: _CA_NOACK—Bus Command Address No-Ack
Commander did not receive an acknowledgment command/address. Probable
causes are:
– A programming error, software fault (addressed nonexistent address)
– A bus buffer failure on the bus commander
• By responders: _CA_PAR—Bus Command/Address Parity Error
Responder detected a parity error during the Command/Address cycle.
The bus was corrupted by commander module (I/O or CPU), backplane, or
responder module (I/O, memory, or CPU).
4–12 Error Log Analysis
U/ERF Bit-to-Text Definition
MEM_0 Correctable Error
MEM_1 Correctable Error
MEM_2 Correctable Error
MEM_3 Correctable Error
MEM_0 Chip Sync Error
MEM_1 Chip Sync Error
MEM_2 Chip Sync Error
MEM_3 Chip Sync Error
Module/Notes
MEM_0, Note
8
MEM_1, Note
8
MEM_2, Note
8
MEM_3, Note
8
MEM_0
MEM_1
MEM_2
MEM_3