System Bus Transaction Cycle; Error Logging And Event Log Entry Format - DEC 4000 AXP Service Manual

Nonfatal errors:
• A memory module correctable error occurred
• Correctable B-cache errors were detected while the B-cache was providing
data to the system bus (errors from other CPU)
• Duplicate tag store parity errors occurred
Processor Corrected Machine Check (SCB: 630)
Processor corrected machine checks are caused by B-cache errors that are
detected and corrected by the DECchip 21064 microprocessor. These errors
are nonfatal and result in an error log entry.

4.1.2 System Bus Transaction Cycle

In order to interpret error logs for system bus errors, you need a basic
understanding of the system bus transaction cycle and the function of the
commander, responder, and bystanders.
For any particular bus transaction cycle there is one commander (either CPU or
I/O) that initiates bus transactions and one responder (memory, CPU, or I/O) that
accepts or supplies data in response to a command/address from the system bus
commander. A bystander is a system bus node (CPU, I/O, or memory) that is not
addressed by a current system bus commander.
There are four system bus transaction types: read, write, exchange, and nut.
• Read and write transactions consist of a command/address cycle followed by
two data cycles.
• Exchange transactions are used to replace the cache block when a cache block
resource conflict occurs. They consist of a command/address cycle followed by
four data cycles: two writes and two reads.
• Nut transactions consist of a command/address cycle and two dummy data
cycles for which no data is transferred.
For more information, refer to the DEC 4000 Model 600 Series Technical Manual.

4.2 Error Logging and Event Log Entry Format

The OpenVMS AXP and DEC OSF/1 error handlers can generate several entry
types. All error entries, with the exception of correctable memory errors, are
logged immediately. Entries can be of variable length based on the number of
registers within the entry.
4–4 Error Log Analysis