Ram Control Register (Ramcr) - Renesas F-ZTAT H8 Series Hardware Manual

19.3.4

RAM Control Register (RAMCR)

The RAM control register (RAMCR) enables flash-memory updates to be emulated in RAM, and
indicates flash memory errors.
Bit 7
FLER
Initial value 0
Read/Write R
Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was
being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode. *
Bit 7: FLER Description
Flash memory is not write/erase-protected (is not in error protect mode *
0
[Clearing condition]
Reset or hardware standby mode
1 Indicates that an error occurred while flash memory was being programmed or
erased, and error protection *
[Setting conditions]
Flash memory was read *
or instruction fetch, but not including reading of a RAM area overlapped onto
flash memory).
A hardware exception-handling sequence (other than a reset, trace exception,
invalid instruction, trap instruction, or zero-divide exception) was executed just
before programming or erasing.
The SLEEP instruction (for transition to sleep mode or software standby mode)
was executed during programming or erasing.
A bus was released during programming or erasing.
Notes: 1. For details, see section 19.5.8, Protect Modes.
2. The read data has undetermined values.
Bits 6 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—RAM Select (RAMS)*: Is used with bits 2 to 0 to reassign an area to RAM (see table
19.6). When bit 3 is set, all flash-memory blocks are protected from programming and erasing,
regardless of the values of bits 2 to 0.
Section 19 Flash Memory (H8/3048F: Dual Power Supply (V
6 5
— —
1 1
— —
2
while being programmed or erased (including vector
4 3
— RAMS RAM2
1 0
— R/W
1
is in effect
Rev. 7.00 Sep 21, 2005 page 595 of 878
= 12 V))
PP
2 1
RAM1 RAM0
0 0
R/W R/W R/W
1
(Initial value)
REJ09B0259-0700
0
0
1
)