User Manuals: Xilinx RocketIO XC2VP7 FPGA Circuit

Manuals and User Guides for Xilinx RocketIO XC2VP7 FPGA Circuit. We have 2 Xilinx RocketIO XC2VP7 FPGA Circuit manuals available for free PDF download: User Manual

Xilinx RocketIO XC2VP7 User Manual (156 pages)

Brand: Xilinx | Category: Transceiver | Size: 1 MB

User Guide
1
Table of Contents
7
Schedule of Figures

13
Schedule of Tables

15
Preface: about this Guide

17
- Rocketio Features
  
  17
- Guide Contents
  
  17
- For more Information
  
  18
- Additional Resources
  
  18
- Conventions
  
  19
  - Port and Attribute Names
    19
  - Typographical
    19
  - Online Document
    20
Chapter 1 : Rocketio Transceiver Overview

21
- Basic Architecture and Capabilities
  
  21
- Rocketio Transceiver Instantiations
  
  23
  - HDL Code Examples
    23
- List of Available Ports
  
  24
- Primitive Attributes
  
  29
- Modifiable Primitives
  
  34
- Byte Mapping
  
  38
Chapter 2: Digital Design Considerations

39
- Clocking
  
  39
  - Clock Signals
    39
    
    Brefclk
    41
  - Clock Ratio
    42
  - Digital Clock Manager (DCM) Examples
    42
    
    Example 1A: Two-Byte Clock with DCM
    43
    
    Example 1B: Two-Byte Clock Without DCM
    46
    
    Example 2: Four-Byte Clock
    46
    
    Example 3: One-Byte Clock
    50
  - Half-Rate Clocking Scheme
    54
  - Multiplexed Clocking Scheme with DCM
    55
  - Multiplexed Clocking Scheme Without DCM
    55
  - Rxrecclk
    56
  - Clock Dependency
    56
  - Data Path Latency
    57
- Reset/Power down
  
  57
- 8B/10B Encoding/Decoding
  
  60
  - Overview
    60
    
    8B/10B Encoder
    60
    
    8B/10B Decoder
    60
  - Ports and Attributes
    61
    
    Txbypass8B10B, Rx_Decode_Use
    61
    
    Txchardispval, Txchardispmode
    62
    
    Txcharisk
    63
    
    Txrundisp
    63
    
    Txkerr
    63
    
    Rxcharisk, Rxrundisp
    63
    
    Rxdisperr
    64
    
    Rxnotintable
    64
  - Vitesse Disparity Example
    64
    
    Transmitting Vitesse Channel Bonding Sequence
    64
    
    Receiving Vitesse Channel Bonding Sequence
    65
  - 8B/10B Bypass Serial Output
    65
  - 8B/10B Serial Output Format
    66
  - HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
    66
- SERDES Alignment
  
  67
  - Overview
    67
    
    Serializer
    67
    
    Deserializer
    67
  - Ports and Attributes
    67
    
    Align_Comma_Msb
    67
    
    Enpcommaalign, Enmcommaalign
    68
    
    Rocketio™ Transceiver User Guide Www.xilinx.com
    69
    
    Pcomma_Detect
    70
    
    Mcomma_Detect
    70
    
    Comma_10B_Mask
    70
    
    Pcomma_10B_Value
    70
    
    Mcomma_10B_Value
    70
    
    Dec_Mcomma_Detect Dec_Valid_Comma_Only
    70
    
    Rxrealign
    70
    
    Dec_Pcomma_Detect
    71
    
    Dec_Mcomma_Detect
    71
    
    Dec_Valid_Comma_Only
    71
    
    Rxchariscomma
    71
    
    Rxcommadet
    71
- Clock Recovery
  
  71
  - Overview
    71
    
    Clock Synthesizer
    71
    
    Clock and Data Recovery
    72
  - Clock Correction
    72
  - Ports and Attributes
    73
    
    Clk_Correct_Use
    73
    
    Rx_Buffer_Use
    74
    
    Clk_Cor_Seq_
    74
    
    Clk_Cor_Seq_Len
    75
    
    Clk_Cor_Insert_Idle_Flag
    75
    
    Clk_Cor_Keep_Idle
    75
    
    Clk_Cor_Repeat_Wait
    75
- Synchronization Logic
  
  76
  - Overview
    76
  - Ports and Attributes
    76
    
    Rxclkcorcnt
    76
    
    Rx_Los_Invalid_Incr Rx_Los_Threshold
    77
    
    Rx_Los_Threshold
    78
- Channel Bonding (Channel Alignment)
  
  79
  - Overview
    79
  - Channel Bonding (Alignment) Operation
    80
  - Ports and Attributes
    81
    
    Chan_Bond_Mode
    81
    
    Enchansync
    81
    
    Chan_Bond_One_Shot
    81
    
    Chan_Bond_Seq_
    81
    
    Chan_Bond__Seq_Len
    81
    
    Chan_Bond_Seq_2_Use
    81
    
    Chan_Bond_Wait
    82
    
    Chan_Bond_Offset
    82
    
    Chan_Bond_Limit
    82
    
    Chbonddone
    83
    
    Chbondi, Chbondo
    83
    
    Rxclkcorcnt, Rxlossofsync
    83
  - Troubleshooting
    83
- CRC (Cyclic Redundancy Check)
  
  84
  - Overview
    84
    
    CRC Operation
    84
    
    CRC Generation
    84
    
    CRC Latency
    85
  - Ports and Attributes
    85
    
    Tx_Crc_Use
    85
    
    Rx_Crc_Use
    85
    
    Crc_Format
    85
    
    Crc_Start_Of_Packet
    88
    
    Crc_End_Of_Packet
    88
    
    Rxcheckingcrc, Rxcrcerr
    88
    
    Txforcecrcerr, Tx_Crc_Force_Value
    89
  - Rocketio CRC Support Limitations
    89
- Fabric Interface (Buffers)
  
  89
  - Overview: Transmitter and Elastic (Receiver) Buffers
    89
    
    Transmitter Buffer (FIFO)
    89
    
    Receiver Buffer
    89
  - Ports and Attributes
    90
    
    Txbuferr
    90
    
    Tx_Buffer_Use
    90
    
    Rxbufstatus
    90
    
    Rx_Buffer_Use
    90
- Miscellaneous Signals
  
  90
  - Tx_Data_Width
    90
  - Serdes_10B
    90
  - Termination_Imp
    91
    
    Rxpolarity Txinhibit
    91
    
    Tx_Diff_Ctrl Pre_Emphasis
    91
  - Loopback
    91
- Other Important Design Notes
  
  93
  - Receive Data Path 32-Bit Alignment
    93
  - Bit Alignment Design
    95
    
    Verilog
    95
    
    Vhdl
    98
Chapter 3 : Analog Design Considerations

103
- Serial I/O Description
  
  103
- Pre-Emphasis Techniques
  
  104
  - Rocketio™ Transceiver User Guide Www.xilinx.com
    105
- Differential Receiver
  
  107
- Jitter
  
  107
  - Clock and Data Recovery
    108
- PCB Design Requirements
  
  109
  - Power Conditioning
    109
    
    Voltage Regulator Selection and Use
    109
    
    Termination Voltage
    110
    
    Passive Filtering
    111
  - High-Speed Serial Trace Design
    115
    
    Routing Serial Traces
    115
    
    Differential Trace Design
    116
    
    AC and DC Coupling
    117
  - Reference Clock
    119
    
    Epson EG-2121CA 2.5V (LVPECL Outputs)
    119
    
    Pletronics LV1145B (LVDS Outputs)
    119
  - Powering the Rocketio Transceivers
    120
- Other Important Design Notes
  
  120
  - Pin Connections on the Unused Rocketio Transceivers
    120
  - The POWERDOWN Port
    120
Chapter 4 : Simulation and Implementation

121
- Simulation Models
  
  121
  - Smartmodels
    121
  - Hspice
    121
- Implementation Tools
  
  121
- MGT Package Pins
  
  123
Appendix A: Rocketio Transceiver Timing Model

129
- Timing Parameters
  
  129
  - Setup/Hold Times of Inputs Relative to Clock
    129
  - Clock to Output Delays
    129
  - Clock Pulse Width
    130
- Timing Parameter Tables and Diagram
  
  130
Appendix B: 8B/10B Valid Characters

135
- Valid Data Characters
  
  135
- Valid Control Characters (K-Characters)
  
  143
Appendix C: Related Online Documents

145
Index

153

Xilinx RocketIO XC2VP7 User Manual (152 pages)

Brand: Xilinx | Category: Transceiver | Size: 1 MB

User Guide
1
Table of Contents
7
Schedule of Figures

13
Schedule of Tables

15
Preface: about this Guide

17
- Rocketio Features
  
  17
- Guide Contents
  
  17
- For more Information
  
  18
- Additional Resources
  
  18
- Conventions
  
  19
  - Port and Attribute Names
    19
  - Typographical
    19
  - Online Document
    20
Chapter 1 : Rocketio Transceiver Overview

21
- Basic Architecture and Capabilities
  
  21
- Rocketio Transceiver Instantiations
  
  23
  - HDL Code Examples
    23
- List of Available Ports
  
  24
- Primitive Attributes
  
  28
- Modifiable Primitives
  
  33
- Byte Mapping
  
  37
Chapter 2: Digital Design Considerations

39
- Clocking
  
  39
  - Clock Signals
    39
    
    Brefclk
    41
  - Clock Ratio
    43
  - Digital Clock Manager (DCM) Examples
    43
    
    Example 1A: Two-Byte Clock with DCM
    44
    
    Example 1B: Two-Byte Clock Without DCM
    47
    
    Example 2: Four-Byte Clock
    47
    
    Example 3: One-Byte Clock
    51
  - Half-Rate Clocking Scheme
    55
  - Multiplexed Clocking Scheme with DCM
    56
  - Multiplexed Clocking Scheme Without DCM
    56
  - Rxrecclk
    57
  - Clock Dependency
    57
  - Data Path Latency
    57
- Reset/Power down
  
  58
- 8B/10B Encoding/Decoding
  
  61
  - Overview
    61
    
    8B/10B Decoder
    61
    
    8B/10B Encoder
    61
  - Ports and Attributes
    62
    
    Txbypass8B10B, Rx_Decode_Use
    62
    
    Txchardispval, Txchardispmode
    63
    
    Rxcharisk, Rxrundisp
    64
    
    Txcharisk
    64
    
    Txkerr
    64
    
    Txrundisp
    64
    
    Rxdisperr
    65
    
    Rxnotintable
    65
  - Vitesse Disparity Example
    65
    
    Transmitting Vitesse Channel Bonding Sequence
    65
    
    Receiving Vitesse Channel Bonding Sequence
    66
  - 8B/10B Bypass Serial Output
    66
  - 8B/10B Serial Output Format
    67
  - HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
    67
- SERDES Alignment
  
  68
  - Overview
    68
    
    Deserializer
    68
    
    Serializer
    68
  - Ports and Attributes
    68
    
    Align_Comma_Msb
    68
    
    Enmcommaalign
    69
    
    Enpcommaalign
    69
    
    Enpcommaalign Enmcommaalign
    69
    
    Comma_10B_Mask, Pcomma_10B_Value, Mcomma_10B_Value
    71
    
    Dec_Mcomma_Detect Dec_Valid_Comma_Only
    71
    
    Mcomma_Detect
    71
    
    Pcomma_Detect
    71
    
    Rxrealign
    71
    
    Dec_Mcomma_Detect
    72
    
    Dec_Pcomma_Detect
    72
    
    Dec_Valid_Comma_Only
    72
    
    Rxchariscomma
    72
    
    Rxcommadet
    72
- Clock Recovery
  
  72
  - Overview
    72
    
    Clock and Data Recovery
    72
    
    Clock Synthesizer
    72
  - Clock Correction
    73
  - Ports and Attributes
    74
    
    Clk_Correct_Use
    74
    
    Rx_Buffer_Use
    74
    
    Clk_Cor_Keep_Idle Clk_Cor_Repeat_Wait
    75
    
    Clk_Cor_Seq_
    75
    
    Clk_Cor_Insert_Idle_Flag
    76
    
    Clk_Cor_Keep_Idle
    76
    
    Clk_Cor_Repeat_Wait
    76
- Synchronization Logic
  
  76
  - Overview
    76
  - Ports and Attributes
    77
    
    Rxclkcorcnt
    77
    
    Rx_Loss_Of_Sync_Fsm
    77
    
    Rx_Los_Invalid_Incr
    77
    
    Rx_Los_Threshold
    77
    
    Rxlossofsync
    78
- Channel Bonding (Channel Alignment)
  
  79
  - Overview
    79
  - Channel Bonding (Alignment) Operation
    80
  - Ports and Attributes
    81
    
    Chan_Bond_Mode
    81
    
    Chan_Bond_One_Shot
    81
    
    Chan_Bond_Seq_
    81
    
    Chan_Bond_Seq_2_Use
    81
    
    Chan_Bond__Seq_Len
    81
    
    Enchansync
    81
    
    Chan_Bond_Limit
    82
    
    Chan_Bond_Offset
    82
    
    Chan_Bond_Wait = 8
    82
    
    Chbonddone
    82
    
    Chbondi, Chbondo
    83
    
    Rxclkcorcnt, Rxlossofsync
    83
  - Troubleshooting
    83
- CRC (Cyclic Redundancy Check)
  
  83
  - Overview
    83
    
    CRC Operation
    83
    
    CRC Generation
    84
    
    CRC Latency
    84
  - Ports and Attributes
    85
    
    Crc_Format
    85
    
    Rx_Crc_Use
    85
    
    Tx_Crc_Use
    85
    
    Crc_End_Of_Packet
    88
    
    Crc_Start_Of_Packet
    88
    
    Rxcheckingcrc, Rxcrcerr
    88
    
    Txforcecrcerr, Tx_Crc_Force_Value
    88
  - Rocketio CRC Support Limitations
    88
- Fabric Interface (Buffers)
  
  89
  - Overview: Transmitter and Elastic (Receiver) Buffers
    89
    
    Receiver Buffer
    89
    
    Transmitter Buffer (FIFO)
    89
  - Ports and Attributes
    89
    
    Rxbufstatus
    89
    
    Txbuferr
    89
    
    Tx_Buffer_Use
    89
    
    Rx_Buffer_Use
    90
- Miscellaneous Signals
  
  90
  - Ports and Attributes
    90
    
    Serdes_10B
    90
    
    Termination_Imp
    90
    
    Tx_Data_Width
    90
    
    Loopback
    91
    
    Rxpolarity Txinhibit
    91
    
    Tx_Diff_Ctrl Pre_Emphasis
    91
- Other Important Design Notes
  
  92
- Other Important Design Notes
  
  93
  - Bit Alignment Design
    94
    
    Verilog
    94
    
    Vhdl
    97
Chapter 3 : Analog Design Considerations

101
- Serial I/O Description
  
  101
- Pre-Emphasis Techniques
  
  102
- Differential Receiver
  
  105
- Jitter
  
  105
  - Clock and Data Recovery
    106
- PCB Design Requirements
  
  107
  - Power Conditioning
    107
    
    Voltage Regulation
    107
    
    Passive Filtering
    109
  - High-Speed Serial Trace Design
    112
    
    Routing Serial Traces
    112
    
    Differential Trace Design
    113
    
    AC and DC Coupling
    114
  - Reference Clock
    116
    
    Epson EG-2121CA 2.5V (LVPECL Outputs)
    116
    
    Pletronics LV1145B (LVDS Outputs)
    116
  - Powering the Rocketio Transceivers
    117
  - Other Important Design Notes
    117
  - The POWERDOWN Port
    117
Chapter 4 : Simulation and Implementation

119
- Simulation Models
  
  119
  - Smartmodels
    119
  - Hspice
    119
- Implementation Tools
  
  119
- MGT Package Pins
  
  121
Appendix A: Rocketio Transceiver Timing Model

127
- Timing Parameters
  
  127
  - Setup/Hold Times of Inputs Relative to Clock
    127
  - Clock to Output Delays
    127
  - Clock Pulse Width
    128
- Timing Parameter Tables and Diagram
  
  128
Appendix B: 8B/10B Valid Characters

133
- Valid Data Characters
  
  133
- Valid Control Characters (K-Characters)
  
  141
Appendix C: Related Online Documents

143
Index

149
- Receive Data Path 32-Bit Alignment
  150

Xilinx Categories

Motherboard Computer Hardware Microcontrollers Transceiver Controller

More Xilinx Manuals

User Manuals: Xilinx RocketIO XC2VP7 FPGA Circuit

Xilinx RocketIO XC2VP7 User Manual (156 pages)

Table of Contents

Schedule of Figures

Schedule of Tables

Preface: about this Guide

Rocketio Features

Guide Contents

For more Information

Additional Resources

Conventions

Chapter 1 : Rocketio Transceiver Overview

Basic Architecture and Capabilities

Rocketio Transceiver Instantiations

List of Available Ports

Primitive Attributes

Modifiable Primitives

Byte Mapping

Chapter 2: Digital Design Considerations

Clocking

Reset/Power down

8B/10B Encoding/Decoding

SERDES Alignment

Clock Recovery

Synchronization Logic

Channel Bonding (Channel Alignment)

CRC (Cyclic Redundancy Check)

Fabric Interface (Buffers)

Miscellaneous Signals

Other Important Design Notes

Chapter 3 : Analog Design Considerations

Serial I/O Description

Pre-Emphasis Techniques

Differential Receiver

Jitter

PCB Design Requirements

Other Important Design Notes

Chapter 4 : Simulation and Implementation

Simulation Models

Implementation Tools

MGT Package Pins

Appendix A: Rocketio Transceiver Timing Model

Timing Parameters

Timing Parameter Tables and Diagram

Appendix B: 8B/10B Valid Characters

Valid Data Characters

Valid Control Characters (K-Characters)

Appendix C: Related Online Documents

Application Notes

Characterization Reports

White Papers

Index