Xilinx virtex-5 fpga User Manual
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Xilinx virtex-5 fpga User Manual

Xilinx virtex-5 fpga User Manual

Rocketio gtp transceiver ibis-ami signal integrity simulation kit
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Virtex-5 FPGA RocketIO
GTP Transceiver IBIS-AMI
Signal Integrity Simulation
Kit User Guide
for SiSoft Quantum Channel Designer
UG587 (v1.1) June 21, 2012

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Summary of Contents for Xilinx virtex-5 fpga

  • Page 1 Virtex-5 FPGA RocketIO GTP Transceiver IBIS-AMI Signal Integrity Simulation Kit User Guide for SiSoft Quantum Channel Designer UG587 (v1.1) June 21, 2012...

  • Page 2: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

  • Page 3: Table Of Contents

    ............5 Chapter 1: Virtex-5 FPGA GTP Transceiver IBIS-AMI SIS Kit Introduction .
  • Page 4 Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...

  • Page 5: Preface: About This Guide

    This manual contains the following chapters: • Chapter 1, Virtex-5 FPGA GTP Transceiver IBIS-AMI SIS Kit, explains how to install, configure, and use SiSoft Quantum Channel Designer to simulate Virtex-5 FPGA RocketIO transceivers. • Appendix A, HSPICE and Quantum Channel Designer/IBIS-AMI Correlation Results, explains how the correlation results were derived and displays results.
  • Page 6 Preface: About This Guide www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...

  • Page 7: Chapter 1: Virtex-5 Fpga Gtp Transceiver Ibis-Ami Sis Kit

    Results are documented with waveform plots. Additional information on the models, ports, and options can be obtained from UG196, Virtex-5 FPGA RocketIO GTP Transceiver User Guide. Additional information regarding the Quantum Channel Designer can be obtained from the SiSoft Quantum Channel Designer User Guide (provided with the SIS Kit installation).

  • Page 8: Installation And Requirements

    (used for network characterization) and a corresponding algorithmic model (used for statistical and time-domain analysis). The receiver model includes the Virtex-5 FPGA GTP peaking filter. S-parameter data is included for the Xilinx package (transmit and receive signals), along with sample channel data for 22-inch, 36-inch, and 56-inch links.

  • Page 9: Transfer Nets

    T2_RX_ONLY: This transfer net has an ideal transmitter driving the GTP receiver model with the Xilinx package. This transfer net used to evaluate a test setup driving into the receiver IP. The transmitter model should be replaced with a model of the stimulus equipment used, and the 0.001...

  • Page 10: Libraries

    (either as a single block of S parameters or as a collection of individual schematic elements) to simulate the behavior of the Xilinx IP with the channel. In this transfer net, the aggressors are quiet.

  • Page 11: Ibis-Ami Models

    Ideal receiver AMI model SiSoft_AMI_Rx.dll Rx_Probe.ami Package Models The package models used in this kit are based on Xilinx S-parameter data. These models provide typical case data and can be replaced by package models for specific packages and applications. Table 1-7 lists the package models and SPICE sub-circuits used in the kit.

  • Page 12: Clock Domains

    This parameter controls the output’s voltage swing. Allowable settings are: “000: 1100mV” “001: 1050mV” “010: 1000mV” TX_Strength (TXDIFFCTRL) “011: 900mV” “100: 800mV” “101: 600mV” “110: 400mV” : 0mV” “111 www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...

  • Page 13: Getting Started

    Notes: The TX parameters are based on TX_DIFF_BOOST = TRUE Getting Started For a review of the kit, refer to the Virtex-5 FPGA GTP SiSoft IBIS-AMI QuickStart video and other videos on the eLearning page of the SiSoft website: http://www.sisoft.com Note: To view the video, SiSoft eLearning accounts are required.
  • Page 14 Getting Started www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...

  • Page 15: Appendix A: Hspice And Quantum Channel Designer/Ibis-Ami Correlation Results

    • Three power levels (400 mV, 800 mV, and 1,100 mV) • Three equalization settings (0%, 18.5%, and 52% de-emphasis) • Three operating corners: • Slow (SS) Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012...

  • Page 16: Correlation Results

    Figure A-10, page Simulation waveforms from the HSPICE transistor level model are shown in red. Simulation results using Quantum Channel Designer and the Virtex-5 FPGA GTP TX IBIS-AMI model are shown in blue. Blue waveforms are always on top. When the red waveform is not visible, it is hidden by the IBIS-AMI waveform (i.e., the match is good).
  • Page 17 Red = HSPICE Blue = QCD Strength = 6 150.0 100.0 50.0 -50.0 -100.0 -150.0 Time (ns) UG587_aA_03_021810 Figure A-3: 100 wline, 400 mV Output Setting, SS, WC, 3 EQ Settings Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012...
  • Page 18 Red = HSPICE Blue = QCD Strength = 0 0.60 0.40 0.20 -0.20 -0.40 -0.60 Time (ns) UG587_aA_05_021810 Figure A-5: 100 wline, 1,100 mV Output Setting, TT, TC, 3 EQ Settings www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...
  • Page 19 Red = HSPICE Blue = QCD Strength = 0 0.60 0.40 0.20 -0.20 -0.40 -0.60 Time (ns) UG587_aA_06_021810 Figure A-6: 100 wline, 1,100 mV Output Setting, SS, WC, 3 EQ Setting Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012...

  • Page 20: Matched (50W And 150 Wline) Case Results

    Red = HSPICE Blue = QCD Strength = 6 200.0 100.0 -100.0 -200.0 Time (ns) UG587_aA_08_021810 Figure A-8: 150 wline, 400 mV Output Setting, TT, TC, 3 EQ Settings www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...
  • Page 21 Red = HSPICE Blue = QCD Strength = 0 0.60 0.40 0.20 -0.20 -0.40 -0.60 Time (ns) UG587_aA_10_021810 Figure A-10: 150 wline, 1100 mV Output Setting, TT, TC, 3 EQ Settings Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012...

  • Page 22: Receiver Correlation

    This section summarizes the simulation results. Simulation waveforms from the HSPICE transistor-level model are presented in blue; simulation results using Quantum Channel Designer and the Virtex-5 FPGA GTP IBIS- AMI RX model are presented in red. Red waveforms are always on top. If the blue waveform is not visible, it is hidden by the IBIS-AMI waveform (i.e., the match is good).
  • Page 23 400.0 300.0 200.0 100.0 -100.0 -200.0 Time (ns) UG587_aA_12_021810 Figure A-12: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 0, Receive Equalization = 1, TT Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012...
  • Page 24 Red = QCD Blue = HSPICE 400.0 300.0 200.0 100.0 -100.0 Time (ns) UG587_aA_14_021810 Figure A-14: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 0, Receive Equalization = 3, TT www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...
  • Page 25 400.0 300.0 200.0 100.0 -100.0 -200.0 Time (ns) UG587_aA_16_021810 Figure A-16: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 0, Receive Equalization = 0, FF Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012...
  • Page 26 Red = QCD Blue = HSPICE 300.0 200.0 100.0 -100.0 -200.0 Time (ns) UG587_aA_18_021810 Figure A-18: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 2, Receive Equalization = 0, FF www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...
  • Page 27 400.0 300.0 200.0 100.0 -100.0 -200.0 Time (ns) UG587_aA_20_021810 Figure A-20: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 1, Receive Equalization = 0, SS Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com UG587 (v1.1) June 21, 2012...
  • Page 28 Red = QCD Blue = HSPICE 200.0 100.0 -100.0 -200.0 Time (ns) UG587_aA_21_021810 Figure A-21: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 2, Receive Equalization = 0, SS www.xilinx.com Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) UG587 (v1.1) June 21, 2012...

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