Reset Signals; Hard Reset (Hreset)-Input; Soft Reset (Sreset)-Input; Processor Status Signals - Motorola MPC750 User Manual

7.2.9.6 Reset Signals
There are two reset signals on the MPC750-hard reset (HRESET) and soft reset
(SRESET). Descriptions of the reset signals are as follows:
7.2.9.6.1 Hard Reset (HRESET)-Input
The hard reset (HRESET) signal must be used at power-on in conjunction with the TRST
signal to properly reset the processor. Following are the state meaning and timing
comments for the HRESET signal.
State Meaning Asserted-Initiates a complete hard reset operation when this input
transitions from asserted to negated. Causes a reset exception as
described in Section 4.5.1, "System Reset Exception (OxOOIOO)."
Output drivers are released to high impedance within five clocks
after the assertion of HRESET.
Negated-Indicates that normal operation should proceed. See
Section 8.7.3, "Reset Inputs."
Timing Comments Assertion-May occur at any time and may be asserted
asynchronously to the MPC750 input clock; must be held asserted
for a minimum of 255 clock cycles after the PLL lock time has been
met. Refer to the MPC750 hardware specifications for further timing
comments.
Negation-May occur any time after the minimum reset pulse width
has been met.
This input has additional functionality in certain test modes.
7.2.9.6.2 Soft Reset (SRESET)-Input
Following are the state meaning and timing comments for the SRESET signal.
State Meaning Asserted- Initiates processing for a reset exception as described in
Section 4.5.1, "System Reset Exception (OxOOlOO)."
Negated-Indicates that normal operation should proceed. See
Section 8.7.3, "Reset Inputs."
Timing Comments Assertion-May occur at any time and may be asserted
asynchronously to the MPC750 input clock. The SRESET input is
negative edge-sensitive.
Negation-May be negated two bus cycles after assertion.
This input has additional functionality in certain test modes.
7.2.9.7 Processor Status Signals
Processor status signals indicate the state of the processor. This includes the memory
reservation signal, machine quiesce control signals, time base enable signal, and
TLBISYNC signal.
Chapter 7. Signal Descriptions
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