Coprocessor System Interface; Coprocessor Classification - Motorola MC68020 User Manual

MC68020/EC020 to begin exception processing. The MC68020/EC020 never generates
coprocessor interface bus cycles with the CpID equal to zero (except via the MOVES
instruction).
CpID codes of 000–101 are reserved for current and future Motorola coprocessors, and
CpID codes of 110–111 are reserved for user-defined coprocessors. The Motorola CpID
code of 001 designates the MC68881 or MC68882 floating-point coprocessor. By default,
Motorola assemblers will use a CpID code of 001 when generating the instruction
operation codes for the MC68881 or MC68882.
The encoding of bits 8–0 of the coprocessor instruction operation word is dependent on
the particular instruction being implemented (refer to 7.2 Coprocessor Instruction
Types).

7.1.4 Coprocessor System Interface

The communication protocol between the main processor and coprocessor necessary to
execute a coprocessor instruction uses a group of interface registers, CIRs, resident
within the coprocessor. By accessing one of the CIRs, the MC68020/EC020 hardware
initiates coprocessor instructions. The coprocessor uses a set of response primitive codes
and format codes defined for the M68000 coprocessor interface to communicate status
and service requests to the main processor through these registers. The CIRs are also
used to pass operands between the main processor and the coprocessor. The CIR set,
response primitives, and format codes are discussed in 7.3 Coprocessor Interface
Register Set and 7.4 Coprocessor Response Primitives.
7.1.4.1 COPROCESSOR CLASSIFICATION. M68000 coprocessors can be classified into
two categories depending on their bus interface capabilities. The first category, non-DMA
coprocessors, consists of coprocessors that always operate as bus slaves. The second
category, DMA coprocessors, consists of coprocessors that operate as bus slaves while
communicating with the main processor across the coprocessor interface. These
coprocessors also have the ability to operate as bus masters, directly controlling the
system bus.
If the operation of a coprocessor does not require a large portion of the available bus
bandwidth or has special requirements not directly satisfied by the main processor, that
coprocessor can be efficiently implemented as a non-DMA coprocessor. Since non-DMA
coprocessors always operate as bus slaves, all external bus-related functions that the
coprocessor requires are performed by the main processor. The main processor transfers
operands from the coprocessor by reading the operand from the appropriate CIR and then
writing the operand to a specified effective address with the appropriate address space
specified on the FC2–FC0. Likewise, the main processor transfers operands to the
coprocessor by reading the operand from a specified effective address (and address
space) and then writing that operand to the appropriate CIR using the coprocessor
interface. The bus interface circuitry of a coprocessor operating as a bus slave is not as
complex as that of a device operating as a bus master.
7-4 M68020 USER'S MANUAL MOTOROLA