Memory System Interface - Motorola MPC8240 User Manual

— Big-and little-endian modes
— PCI agent capability
— PCI bus clock buffers and bus ratios
• DMA controller
• Message unit
— Doorbell registers
— Message registers
— I O support (circular queues)
2
• Embedded programmable interrupt controller (EPIC) with four timers
2
• I C interface

1.4.3 Memory System Interface

The MPC8240 memory interface controls processor and PCI interactions to main memory.
It supports a variety of DRAM, and Flash or ROM configurations as main memory. The
MPC8240 supports fast page mode (FPM), extended data out (EDO) and synchronous
DRAM (SDRAM). The maximum supported memory size is 1 Gbyte of DRAM or
SDRAM and 16 Mbytes of ROM/Flash. SDRAM must comply with the JEDEC SDRAM
specification.
The MPC8240 implements Port X, a memory bus interface that facilitates the connection
of general-purpose I/O devices. The Port X functionality allows the designer to connect
external registers, communication devices, and other such devices directly to the
MPC8240. Some devices may require a small amount of external logic to generate properly
address strobes, chip selects, and other signals.
The MPC8240 is designed to control a 32- or 64-bit data path to main memory DRAM or
SDRAM. For a 32-bit data path, the MPC8240 can be configured to check and generate
byte parity using four parity bits. For a 64-bit data path, the MPC8240 can be configured to
support parity or ECC checking and generation with eight parity/syndrome bits checked
and generated. Note that the data bus width (32- or 64-bit) chosen at reset for the 60x bus
interface is also used for the memory interface.
The MPC8240 supports DRAM or SDRAM bank sizes from 1 to 128 Mbytes and provides
bank start address and end address configuration registers. Note that the MPC8240 does not
support mixed DRAM/SDRAM configurations. The MPC8240 can be configured so that
appropriate row and column address multiplexing occurs according to the accessed
memory bank. Addresses are provided to DRAM and SDRAM through a 13-bit interface
for DRAM and a 14-bit interface for SDRAM.
Two chip selects, one write enable, one output enable, and up to 21 address signals are
provided for ROM/Flash systems.
Chapter 1. Overview
Peripheral Logic Overview
1-13