E.1.2 Powerpc Vea Register Set—Time Base - Motorola MPC8240 User Manual

PowerPC Register Set
Table E-7. BO Operand Encodings (Continued)
BO
1z1zz Branch always.
Notes: The y bit provides a hint about whether a conditional branch is likely to be taken and is used by
some PowerPC implementations to improve performance. Other implementations may ignore the
y bit.
The z indicates a bit that is ignored. The z bits should be cleared (zero), as they may be assigned
a meaning in a future version of the PowerPC UISA.
E.1.2 PowerPC VEA Register Set—Time Base
The PowerPC virtual environment architecture (VEA) defines registers in addition to those
defined by the UISA. The PowerPC VEA register set can be accessed by all software with
either user- or supervisor-level privileges. Figure E-1 provides a graphic illustration of the
PowerPC VEA register set included in the MPC8240.
The PowerPC VEA introduces the time base facility (TB), a 64-bit structure that consists
of two 32-bit registers—time base upper (TBU) and time base lower (TBL), whose contents
are incremented once every four sys_logic_clk cycles on the MPC8240. Note that the time
base registers can be accessed by both user- and supervisor-level instructions. In the context
of the VEA, user-level applications are permitted read-only access to the TB. The OEA
defines supervisor-level access to the TB for writing values to the TB. See Section E.1.3.9,
"Time Base Facility (TB)—OEA; Writing to the Time Base," for more information.
The time base (TB) is shown in Figure E-9.
TBU—Upper 32 bits of time base
0
E.1.2.1 Reading the Time Base
The mftb instruction is used to read the time base. For information on writing the time base,
see Section E.1.3.9, "Time Base Facility (TB)—OEA; Writing to the Time Base."
On 32-bit implementations, it is not possible to read the entire 64-bit time base in a single
instruction. The mftb simplified mnemonic moves from the lower half of the time base
register (TBL) to a GPR, and the mftbu simplified mnemonic moves from the upper half
of the time base (TBU) to a GPR.
Because of the possibility of a carry from TBL to TBU occurring between reads of the TBL
and TBU, a sequence such as the following example is necessary to read the time base on
32-bit implementations:
loop:
mftbu rx
mftb ry
mftbu rz
cmpw rz,rx
bne loop
E-10
31 0
Figure E-9. Time Base (TB)
#load from TBU
#load from TBL
#load from TBU
#see if 'old' = 'new'
#loop if carry occurred
MPC8240 Integrated Processor User's Manual
Description
TBL—Lower 32 bits of time base
31