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When a program exception is taken, instruction fetching resumes at offset Ox00700 from
the physical base address indicated by MSR[IP]. Chapter 6, "Exceptions," in The
Programming Environments Manual describes register settings for this exception.
4.5.8 Floating-Point Unavailable Exception (Ox00800)
The floating-point unavailable exception is implemented as defined in the PowerPC
architecture. A floating-point unavailable exception occurs when no higher priority
exception exists, an attempt is made to execute a floating-point instruction (including
floating-point load, store, or move instructions), and the floating-point available bit in the
MSR is disabled, (MSR[FP]
=
0). Register settings for this exception are described in
Chapter 6, "Exceptions," in The Programming Environments Manual.
When a floating-point unavailable exception is taken, instruction fetching resumes at offset
Ox00800 from the physical base address indicated by MSR[IP].
4.5.9 Decrementer Exception (Ox00900)
The decrementer exception is implemented in the MPC750 as it is defined by the PowerPC
architecture. The decrementer exception occurs when no higher priority exception exists, a
decrementer exception condition occurs (for example, the decrementer register has
completed decrementing), and MSR[EE]
=
1.
In
the MPC750, the decrementer register is
decremented at one fourth the bus clock rate. Register settings for this exception are
described in Chapter 6, "Exceptions," in The Programming Environments Manual.
When a decrementer exception is taken, instruction fetching resumes at offset Ox00900
from the physical base address indicated by MSR[IP].
4.5.10 System Call Exception (OxOOCOO)
A system call exception occurs when a System Call (sc) instruction is executed.
In
the
MPC750, the system call exception is implemented as it is defined in the PowerPC
architecture. Register settings for this exception are described in Chapter 6, "Exceptions,"
in The Programming Environments Manual.
When a system call exception is taken, instruction fetching resumes at offset OxOOCOO from
the physical base address indicated by MSR[IP].
4.5.11 Trace Exception (OxOODOO)
The trace exception is taken if MSR[SE]
=
1 or if MSR[BE]
=
1 and the currently
completing instruction is a branch. Each instruction considered during trace mode
completes before a trace exception is taken. When a trace exception is taken, the values
written to SRRI are implementation-specific; those values for the MPC750 are shown in
Table 4-10.
Chapter 4. Exceptions
4-19
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