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3.6.1 Chip-Select Logic Key Features
Key features of the chip-select logic are as follows:
• Four Programmable Chip-Select Lines
• Various Block Sizes: 8K, 16K, 32K, 64K, 128K, 256K, 512K, 1M, 2M, 4M,
8M, and 16M Bytes
• Read-Only, Write-Only or Read-Write Select
• Internal DTACK Generation with Wait-State Options
• Default Line (CSO) to Select an SK-Boot ROM Containing the Reset Vector
and Initial Program
3.6.2 Chip-Select Registers
Each of the four chip-select units has two registers that define its specific
operation. These registers include a 16-bit base register (BR) and a 16-bit
option register (OR). These registers may be modified by the M68000 core.
3.6.2.1 BASE REGISTER (BR3-BRO).
These 16-bit registers consist of a base ad-
dress field, a read-write bit, and a function code field.
3-42
15
13
12
FC2-FCO
BASE ADDRESS IA23-A13)
EN - Enable ..
O =The chip-select line is disabled.
1 =The chip-select line is enabled.
After system reset, only CSO is enabled; CS3-CS1 are disabled.
RW -
Read/Write
0 =The chip-select line is asserted for read operations only.
1 =The chip-select line is asserted for write operations only.
After system reset, this bit defaults to zero (read-only operation).
NOTE
This bit can be masked and ignored by the read-write compare logic,
as determined by MRW in the OR. The line is then asserted for both
read and write cycles.
On write protect violation cycles (RW = 0 and MRW = 1 ), BERR will be gen-
erated, and WPV will be set.
MC68302 USER'S MANUAL
MOTOROLA
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