Port A Data Direction Register (Paddr) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Data Direction Registers
the appropriate control register. If a GPIO line changes from an input to an output, the initial
data on that pin is the last data written to the latch by the corresponding data register.
At system reset, these register bits are all cleared, configuring all port I/O lines as general
purpose inputs. Bootstrap software must write an appropriate value into the data direction
register to configure GPIO port signals as outputs. When these registers are first written, any
internal pullups on the corresponding I/O pins are disabled.
A detailed description is provided only for data direction register A (PADDR). The control
bits in all three registers operate in the same manner.

17.3.1 Port A Data Direction Register (PADDR)

The PADDR determines the signal direction of each parallel port pin programmed as a
GPIO port in the PACNT.
15
Field
Reset
R/W
Addr
Figure 17-4. Port A Data Direction Register (PADDR)
Bits Name
15–0 PADDR
17.3.2 Port B Data Direction Register (PBDDR)
The PBDDR determines the signal direction of each parallel port pin programmed as a
GPIO port in the PBCNT.
15
Field
Reset
R/W
Addr
Figure 17-5. Port B Data Direction Register (PBDDR)
17-10
0000_0000_0000_0000
Table 17-9. PADDR Field Descriptions
Data direction bits. Each data direction bit selects the direction of the signal as follows:
0 Signal is defined as an input.
1 Signal is defined as an output.
0000_0000_0000_0000
MCF5272 User's Manual
PADDR
Read/Write
MBAR + 0x0084
Description
PBDDR
Read/Write
MBAR + 0x008C
0
0