Instruction Timing - Motorola DigitalDNA ColdFire MCF5272 User Manual

Table 2-7. User-Mode Instruction Set Summary (Continued)
Instruction Operand Syntax
TRAPF None
#<data>
TST <ea>y
UNLK Ax
WDDATA <ea>y
1
By default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode
execution by setting CSR[UHE].
Table 2-8 describes supervisor-mode instructions.
Table 2-8. Supervisor-Mode Instruction Set Summary
Instruction Operand Syntax Operand Size
CPUSHL (bc),(Ax)
1
HALT none
MOVE from SR SR, Dx
MOVE to SR Dy,SR
#<data>,SR
MOVEC Ry,Rc
RTE None
STOP #<data>
WDEBUG <ea-2>y
1
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].

2.7 Instruction Timing

The timing data presented in this section assumes the following:
• The OEP is loaded with the opword and all required extension words at the
beginning of each instruction execution. This implies that the OEP spends no time
waiting for the IFP to supply opwords and/or extension words.
• The OEP experiences no sequence-related pipeline stalls. For the MCF5272,the
most common example of this type of stall involves consecutive store operations,
excluding the MOVEM instruction. For all store operations (except MOVEM),
Operand Size
Unsized PC + 2 → PC
.W PC + 4 → PC
.L PC + 6 → PC
.B,.W,.L Set condition codes
Unsized Ax →SP; (SP) → Ax; SP + 4 → SP
.B,.W,.L <ea>y →DDATA port
Unsized Invalidate instruction cache line
Unsized Enter halted state
.W SR → Dx
.W Source → SR
.L Ry → Rc
Rc
0x002
0x004
0x005
0x801
0xC00 ROM base address register (ROMBAR)
0xC04 RAM base address register (RAMBAR)
0xC0F Module base address register (MBAR)
Unsized (SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield  SP
.W Immediate data → SR; enter stopped state
.L <ea-2>y → debug module
Chapter 2. ColdFire Core
Operation
Operation
Register Definition
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Vector base register (VBR)
Instruction Timing
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