Instruction Timing - Motorola MPC750 User Manual

1.9 Instruction Timing
The MPC750 is a pipelined, superscalar processor. A pipelined processor is one in which
instruction processing is divided into discrete stages, allowing work to be done on different
instructions in each stage. For example, after an instruction completes one stage, it can pass
on to the next stage leaving the previous stage available to the subsequent instruction. This
improves overall instruction throughput.
A superscalar processor is one that issues multiple independent instructions into separate
execution units, allowing instructions to execute in parallel. The MPC750 has six
independent execution units, two for integer instructions, and one each for floating-point
instructions, branch instructions, load/store instructions, and system register instructions.
Having separate GPRs and FPRs allows integer, floating-point calculations, and load and
store operations to occur simultaneously without interference. Additionally, rename buffers
are provided to allow operations to post execution results for use by subsequent instructions
without committing them to the architected FPRs and GPRs.
As shown in Figure 1-6, the common pipeline of the MPC750 has four stages through
which all instructions must pass-fetch, decode/dispatch, execute, and complete/write
back. Some instructions occupy multiple stages simultaneously and some individual
execution units have additional stages. For example, the floating-point pipeline consists of
three stages through which all floating-point instructions must pass.
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Fetch
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Dispatch
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Maximum four-instruction fetch
per clock cycle
Maximum thre e-instruction dispatch
(includes one branch per clock cycle
instruction)
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Ute-stage -;
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Exec
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!
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FPU2 LSUI
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SRU FPU3 lUI IU2 LSU2
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------------------
Maximum two-i
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Complete (Write-Back)
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completion per
Figure 1-6. Pipeline Diagram
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nstruction
clock cycle
Note that Figure 1-6 does not show features, such as reservation stations and rename buffers
that reduce stalls and improve instruction throughput.
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