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Registers
20.9.6.2.3 Control Status Register for Endpoint 0 in Host Mode (USBn_HOST_CSR0)
The control status register for endpoint 0 in host mode (USBn_HOST_CSR0) is a 16-bit register that
provides control and status bits for endpoint 0 when USB controller assumes the role of a host. This
register is shown in
Figure 20-158. Control Status Register for Endpoint 0 in Host Mode (USBn_HOST_CSR0)
15
Reserved
R-0h
7
6
NAK_TIMEOUT
STATUSPKT
W-0-1h
R/W-0-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-175. Control Status Register for Endpoint 0 in Host Mode (USBn_HOST_CSR0) Field
Bits
Field Name
15-12
Reserved
11
DSPING
10
DATATOGWREN
9
DATATOG
8
FLUSHFIFO
7
NAK_TIMEOUT
6
STATUSPKT
5
REQPKT
4
ERROR
3
SETUPPKT
2
RXSTALL
1
TXPKTRDY
0
RXPKTRDY
1954
Universal Serial Bus (USB)
Preliminary
Figure 20-158
and described in
12
11
DSPING
R/W-0-1h
5
4
REQPKT
ERROR
R/W-0-1h
W-0-1h
Descriptions
Description
Reserved
The CPU writes a 1 to the DSPING bit to instruct the core not to issue PING tokens in the
data and status phases of a high-speed control transfer (for use with devices that do not
respond to PING).
Write 1 to this bit to enable the DATATOG bit to be written. This bit is automatically cleared
once the new value is written to DATATOG.
When read, this bit indicates the current state of the EP0 data toggle. If DATATOGWREN
is high, this bit can be written with the required setting of the data toggle. If
DATATOGWREN is low, any value written to this bit is ignored.
Write 1 to this bit to flush the next packet to be transmitted/read from the Endpoint 0 FIFO.
The FIFO pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared. Note:
FLUSHFIFO has no effect unless TXPKTRDY/RXPKTRDY is set.
This bit will be set when endpoint 0 is halted following the receipt of NAK responses for
longer than the time set by the NAKLIMIT0 register. This bit should be cleared to allow the
endpoint to continue.
Set this bit at the same time as the TXPKTRDY or REQPKT bit is set, to perform a status
stage transaction. Setting this bit ensures that the data toggle is set so that a DATA1
packet is used for the Status Stage transaction.
Set this bit to request an IN transaction. It is cleared when RXPKTRDY is set.
This bit is set when three attempts have been made to perform a transaction with no
response from the peripheral. You should clear this bit. An interrupt is generated when this
bit is set.
Set this bit, at the same time as the TXPKTRDY bit is set, to send a SETUP token instead
of an OUT token for the transaction.
This bit is set when a STALL handshake is received. You should clear this bit.
Set this bit after loading a data packet into the FIFO. It is cleared automatically when the
data packet has been transmitted. An interrupt is generated (if enabled) when the bit is
cleared.
This bit is set when a data packet has been received. An interrupt is generated when this
bit is set. Clear this bit by setting the SERV_RXPKTRDY bit.
© 2011, Texas Instruments Incorporated
Table
20-175.
10
DATATOGWREN
W-0-1h
3
2
SETUPPKT
RXSTALL
R/W-0-1h
R/W-0-1h
www.ti.com
9
8
DATATOG
FLUSHFIFO
R/W-0-1h
W-0-1h
1
0
TXPKTRDY
RXPKTRDY
R/W-0-1h
R/W-0-1h
SPRUGX9 – 15 April 2011
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