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20.9.7 FIFOs
This address range provides access to the endpoint FIFOs. Register offset addresses for this block is
20h to 5Fh.
20.9.7.1 Transmit and Receive FIFO Register for Endpoint 0 - 15 (USBn_FIFO0 – USBn_FIFO15)
This address range provides 16 addresses for CPU access to the FIFOs for each endpoint. Writing to
these addresses loads data into the TxFIFO for the corresponding endpoint. Reading from these
addresses unloads data from the RxFIFO for the corresponding endpoint. The address range is 20h –
5Fh and the FIFOs are located on 32-bit double-word boundaries (endpoint 0 at 20h, endpoint 1 at
24h ... Endpoint 15 at 5Ch).
Note 1: Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of
access is allowed provided the data accessed is contiguous. However, all the transfers associated with
one packet must be of the same width so that the data is consistently byte-, word- or
double-word-aligned. The last transfer may however contain fewer bytes than the previous transfers in
order to complete an odd-byte or odd-word transfer.
Note 2: Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support
either single-packet or doublepacket buffering. However, burst writing of multiple packets is not
supported as flags need to be set after each packet is written.
Note 3: Following a STALL response or a Tx strike out error on dndpoint 1 – 15, the associated FIFO is
completely flushed.
The transmit and receive FIFO register for endpoint 0 - 15 (USBn_FIFO0 – USBn_FIFO15) is shown in
Figure 20-173
and described in
Figure 20-173. Transmit and Receive FIFO Register for Endpoint 0 - 15 (USBn_FIFO0 –
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-190. FIFOs: Transmit and Receive FIFO Register for Endpoint 0 - 15 (USBn_FIFO0 –
Bit
Field
31-0
DATA
20.9.7.2 Additional Control and Configuration Registers
Table 20-191
lists the additional Control and Configuration registers.
Core Address Offset
SPRUGX9 – 15 April 2011
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Preliminary
Table
20-190.
USBn_FIFO15)
R/W-0-FFFF
USBn_FIFO15) Field Descriptions
Description
Writing to these addresses loads data into the Transmit FIFO for the corresponding
endpoint. Reading from these addresses unloads data from the Receive FIFO for the
corresponding endpoint.
Table 20-191. Additional Control and Configuration Registers
60h
62h
63h
64h
66h
6Ch
© 2011, Texas Instruments Incorporated
DATA
FFFFh
Control and Configuration Registers
Device Control Register
Transmit Endpoint FIFO Size Register
Receive Endpoint FIFO Size Register
Transmit Endpoint FIFO Address Register
Receive Endpoint FIFO Address Register
Hardware Version Register
Registers
0
1969
Universal Serial Bus (USB)
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