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20.9.6.1.11 Register to Enable the USB 2.0 Test Modes (USBn_TESTMODE)
The register to enable the USB 2.0 test modes (USBn_TESTMODE) is an 8-bit register that is primarily
used to put the USB controller into one of the four test modes for high-speed operation described in the
USB 2.0 specification – in response to a SET FEATURE: TESTMODE command. It is not used in
normal operation.
The register to enable the USB 2.0 test modes is shown in
Table
20-171.
Figure 20-155. Register to Enable the USB 2.0 Test Modes (USBn_TESTMODE)
7
6
FORCE_HOST
FIFO_ACCESS
R/W-0-1h
W-0-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-171. Register to Enable the USB 2.0 Test Modes (USBn_TESTMODE) Field Descriptions
Bits
Field Name
7
FORCE_HOST
6
FIFO_ACCESS
5
FORCE_FS
4
FORCE_HS
3
TEST_PACKET
2
TEST_K
1
TEST_J
0
TEST_SE0_NAK
SPRUGX9 – 15 April 2011
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Preliminary
5
4
FORCE_FS
FORCE_HS
R/W-0-1h
R/W-0-1h
Description
Set this bit to forcibly put the USB controller into Host mode when SESSION bit is set,
regardless of whether it is connected to any peripheral. The controller remains in Host mode
until the session bit is cleared, even if a device is disconnected. And if the FORCE_HOST but
remains set, it re-enters Host mode next time the SESSION bit is set. The operating speed is
determined using the FORCE_HS and FORCE_FS bits.
Set this bit to transfer the packet in EP0 Tx FIFO to EP0 Receive FIFO. It is cleared
automatically.
Set this bit to force the USB controller into full-speed mode when it receives a USB reset.
Set this bit to force the USB controller into high-speed mode when it receives a USB reset.
Set this bit to enter the Test_Packet test mode. In this mode, the USB controller repetitively
transmits a 53-byte test packet on the bus, the form of which is defined in the Universal Serial
Bus Specification Revision 2.0. Note: The test packet has a fixed format and must be loaded
into the endpoint 0 FIFO before the test mode is entered.
Set this bit to enter the Test_K test mode. In this mode, the USB controller transmits a
continuous K on the bus.
Set this bit to enter the Test_J test mode. In this mode, the USB controller transmits a
continuous J on the bus.
Set this bit to enter the Test_SE0_NAK test mode. In this mode, the USB controller remains in
high-speed mode, but responds to any valid IN token with a NAK.
© 2011, Texas Instruments Incorporated
Figure 20-155
and described in
3
2
TEST_PACKET
TEST_K
R/W-0-1h
R/W-0-1h
Registers
1
0
TEST_J
TEST_SE0_NAK
R/W-0-1h
R/W-0-1h
1951
Universal Serial Bus (USB)
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