Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1959

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Table 20-179. Control Status Register for Peripheral Receive Endpoint (USBn_PERI_RXCSR) Field
Bit Field
0 RXPKTRDY
20.9.6.2.8 Control Status Register for Host Receive Endpoint (USBn_HOST_RXCSR)
The control status register for host receive endpoint (USBn_HOST_RXCSR) is a 16-bit register that
provides control and status bits for transfers through the currently-selected Rx endpoint when controller
assumes the role of a host. There is a TXCSR register for each configured Rx endpoint (not including
endpoint 0).
The control status register for host receive endpoint is shown in
Table 20-180.
Figure 20-163. Control Status Register for Host Receive Endpoint (USBn_HOST_RXCSR)
15 14
AUTOCLEAR AUTOREQ
R/W-0-1h R/W-0-1h
7 6
CLRDATATOG RXSTALL
W-0-1h R/W-0-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-180. Control Status Register for Host Receive Endpoint (USBn_HOST_RXCSR) Field
Bit Field
15 AUTOCLEAR
14 AUTOREQ
13 DMAEN
12 DISNYET
11 DMAMODE
10 DATATOGWREN
9 DATATOG
8 Reserved
7 CLRDATATOG
6 RXSTALL
5 REQPKT
SPRUGX9 – 15 April 2011
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Preliminary
Descriptions (continued)
Description
This bit is set when a data packet has been received. You should clear this bit when the
packet has been unloaded from the Receive FIFO. An interrupt is generated when the bit is
set.
13 12
DMAEN DISNYET
R/W-0-1h R/W-0-1h
5 4
REQPKT FLUSHFIFO
R/W-0-1h W-0-1h
Descriptions
Description
DMA Mode: The CPU sets the AUTOCLEAR bit prior to enabling the Rx DMA. CPU
Mode: If the CPU sets the AUTOCLEAR bit, then the RXPKTRDY bit will be
automatically cleared when a packet of RXMAXP bytes has been unloaded from the
Receive FIFO. When packets of less than the maximum packet size are unloaded,
RXPKTRDY will have to be cleared manually.
If the CPU sets the AUTOREQ bit, then the REQPKT bit will be automatically set when
the RXPKTRDY bit is cleared. Note: This bit is automatically cleared when a short
packet is received.
Set this bit to enable the DMA request for the Receive endpoints.
Set this bit to disable the sending of NYET handshakes. When set, all successfully
received Receive packets are ACKED including at the point at which the FIFO becomes
full. Note: This bit only has any effect in high-speed mode, in which mode it should be
set for all Interrupt endpoints.
Always clear this bit to 0.
Write 1 to this bit to enable the DATATOG bit to be written. This bit is automatically
cleared once the new value is written to DATATOG.
When read, this bit indicates the current state of the Receive EP data toggle. If
DATATOGWREN is high, this bit can be written with the required setting of the data
toggle. If DATATOGWREN is low, any value written to this bit is ignored.
Reserved
Write a 1 to this bit to reset the endpoint data toggle to 0.
When a STALL handshake is received, this bit is set and an interrupt is generated. You
should clear this bit.
Write a 1 to this bit to request an IN transaction. It is cleared when RXPKTRDY is set.
© 2011, Texas Instruments Incorporated
Figure 20-163
11 10
DATA
DMAMODE
TOGWREN
R/W-0-1h W-0-1h
3 2
DATAERR_
ERROR
NAKTIMEOUT
R-0-1h R/W-0-1h
Registers
and described in
9 8
DATATOG Reserved
R/W-0-1h R-0h
1 0
FIFOFULL RXPKTRDY
R-0-1h R/W-0-1h
1959
Universal Serial Bus (USB)