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20.9.6.2.2 Control Status Register for Endpoint 0 in Peripheral Mode (USBn_PERI_CSR0)
The control status register for endpoint 0 in peripheral mode (USBn_PERI_CSR0) is a 16-bit register
that provides control and status bits for endpoint 0 when USB controller assumes the role of a
peripheral. This register is shown in
Figure 20-157. Control Status Register for Endpoint 0 in Peripheral Mode (USBn_PERI_CSR0)
15
7
6
SERV_
SERV_
SETUPEND
RXPKTRDY
W-0-1h
W-0-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-174. Control Status Register for Endpoint 0 in Peripheral Mode (USBn_PERI_CSR0)
Bits
Field Name
15-9
Reserved
8
FLUSHFIFO
7
SERV_SETUPEND
6
SERV_RXPKTRDY
5
SENDSTALL
4
SETUPEND
3
DATAEND
2
SENTSTALL
1
TXPKTRDY
0
RXPKTRDY
SPRUGX9 – 15 April 2011
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Preliminary
Figure 20-157
Reserved
R-0h
5
4
SENDSTALL
SETUPEND
W-0-1h
R-0-1h
Field Descriptions
Description
Reserved
Set this bit to flush the next packet to be transmitted/read from the endpoint 0 FIFO. The
FIFO pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared. Note: FLUSHFIFO has
no effect unless TXPKTRDY/RXPKTRDY is set.
Set this bit to clear the SETUPEND bit. It is cleared automatically.
Set this bit to clear the RXPKTRDY bit. It is cleared automatically.
Set this bit to terminate the current transaction. The STALL handshake will be transmitted
and then this bit will be cleared automatically.
This bit will be set when a control transaction ends before the DATAEND bit has been set.
An interrupt is generated, and the FIFO will be flushed at this time. The bit is cleared by the
writing a 1 to the SERV_SETUPEND bit.
Set this bit to 1:
• When setting TXPKTRDY for the last data packet.
• When clearing RXPKTRDY after unloading the last data packet.
• When setting TXPKTRDY for a zero length data packet. It is cleared automatically.
This bit is set when a STALL handshake is transmitted. This bit should be cleared.
Set this bit after loading a data packet into the FIFO. It is cleared automatically when the
data packet has been transmitted. An interrupt is generated (if enabled) when the bit is
cleared.
This bit is set when a data packet has been received. An interrupt is generated when this
bit is set. This bit is cleared by setting the SERV_RXPKTRDY bit.
© 2011, Texas Instruments Incorporated
and described in
Table
20-174.
3
2
DATAEND
SENTSTALL
W-0-1h
R/W-0-1h
Registers
9
8
FLUSHFIFO
W-0-1h
1
0
TXPKTRDY
RXPKTRDY
R/W-0-1h
R-0h
1953
Universal Serial Bus (USB)
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