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Registers
Table 20-180. Control Status Register for Host Receive Endpoint (USBn_HOST_RXCSR) Field
Bit
Field
4
FLUSHFIFO
3
DATAERR_NAKTIMEOUT
2
ERROR
1
FIFOFULL
0
RXPKTRDY
1960
Universal Serial Bus (USB)
Preliminary
Descriptions (continued)
Description
Write a 1 to this bit to flush the next packet to be read from the endpoint Receive FIFO.
The FIFO pointer is reset and the RXPKTRDY bit is cleared. Note: FLUSHFIFO has no
effect unless RXPKTRDY is set. Also note that, if the FIFO is double-buffered,
FLUSHFIFO may need to be set twice to completely clear the FIFO.
When operating in ISO mode, this bit is set when RXPKTRDY is set if the data packet
has a CRC or bit-stuff error and cleared when RXPKTRDY is cleared. In Bulk mode, this
bit will be set when the Receive endpoint is halted following the receipt of NAK
responses for longer than the time set as the NAK Limit by the RXINTERVAL register.
You should clear this bit to allow the endpoint to continue.
The USB controller sets this bit when 3 attempts have been made to receive a packet
and no data packet has been received. You should clear this bit. An interrupt is
generated when the bit is set. Note: This bit is only valid when the transmit endpoint is
operating in Bulk or Interrupt mode. In ISO mode, it always returns zero.
This bit is set when no more packets can be loaded into the Receive FIFO.
This bit is set when a data packet has been received. You should clear this bit when the
packet has been unloaded from the Receive FIFO. An interrupt is generated when the
bit is set.
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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