Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1956

Registers
20.9.6.2.5 Control Status Register for Host Transmit Endpoint (USBn_HOST_TXCSR)
The control status register for host transmit endpoint (USBn_HOST_TXCSR) is a 16-bit register that
provides control and status bits for transfers through the currently-selected Tx endpoint when controller
assumes the role of a host. There is a TXCSR register for each configured Tx endpoint (not including
Endpoint 0).
The control status register for host transmit endpoint is shown in
Figure 20-160.
Figure 20-160. Control Status Register for Host Transmit Endpoint (USBn_HOST_TXCSR)
15 14
AUTOSET Reserved
R/W-0-1h R-0h
7 6
NAK_TIMEOUT CLRDATATOG
R/W-0-1h W-0-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-177. Control Status Register for Host Transmit Endpoint (USBn_HOST_TXCSR) Field
Bits Field Name
15 AUTOSET
14 Reserved
13 MODE
12 DMAEN
11 FRCDATATOG
10 DMAMODE
9 DATATOGWREN
8 DATATOG
7 NAK_TIMEOUT
6 CLRDATATOG
5 RXSTALL
4 SETUPPKT
3 FLUSHFIFO
2 ERROR
1956 Universal Serial Bus (USB)
Preliminary
13 12
MODE DMAEN
R/W-0-1h
5 4
RXSTALL SETUPPKT
R/W-0-1h R/W-0-1h
Descriptions
Description
DMA Mode: The CPU needs to set the AUTOSET bit prior to enabling the Tx DMA. CPU
Mode: If the CPU sets the AUTOSET bit, the TXPKTRDY bit will be automatically set
when data of the maximum packet size (value in TXMAXP) is loaded into the Tx FIFO. If
a packet of less than the maximum packet size is loaded, then the TXPKTRDY bit will
have to be set manually.
Reserved
Set this bit to enable the endpoint direction as Tx, and clear the bit to enable it as Rx.
Note: This bit has any effect only where the same endpoint FIFO is used for both
Transmit and Receive transactions.
Set this bit to enable the DMA request for the Tx endpoint.
Set this bit to force the endpoint data toggle to switch and the data packet to be cleared
from the FIFO, regardless of whether an ACK was received. This can be used by
Interrupt Tx endpoints that are used to communicate rate feedback for Isochronous
endpoints.
This bit should always be set to 1 when the DMA is enabled.
Write 1 to this bit to enable the DATATOG bit to be written. This bit is automatically
cleared once the new value is written to DATATOG.
When read, this bit indicates the current state of the Tx EP data toggle. If
DATATOGWREN is high, this bit can be written with the required setting of the data
toggle. If DATATOGWREN is low, any value written to this bit is ignored.
This bit will be set when the Tx endpoint is halted following the receipt of NAK responses
for longer than the time set as the NAKLIMIT by the TXINTERVAL register. It should be
cleared to allow the endpoint to continue. Note: This is valid only for Bulk endpoints.
Write a 1 to this bit to reset the endpoint data toggle to 0.
This bit is set when a STALL handshake is received. The FIFO is flushed and the
TXPKTRDY bit is cleared (see below). You should clear this bit.
Set this bit at the same time as TXPKTRDY is set, to send a SETUP token instead of an
OUT token for the transaction. Note: Setting this bit also clears the DATATOG bit.
Write a 1 to this bit to flush the next packet to be transmitted from the endpoint Tx FIFO.
The FIFO pointer is reset and the TXPKTRDY bit (below) is cleared. Note: FlushFIFO has
no effect unless the TXPKTRDY bit is set. Also note that, if the FIFO is double-buffered,
FLUSHFIFO may need to be set twice to completely clear the FIFO.
The USB controller sets this bit when 3 attempts have been made to send a packet and
no handshake packet has been received. You should clear this bit. An interrupt is
generated when the bit is set. This is valid only when the endpoint is operating in Bulk or
Interrupt mode.
© 2011, Texas Instruments Incorporated
Figure 20-160
11 10
FRCDATATOG DMAMODE
R/W-0-1h
3 2
FLUSHFIFO ERROR
W-0-1h R/W-0-1h
www.ti.com
and described in
9 8
DATA
DATATOG
TOGWREN
W-0-1h R/W-0-1h
1 0
FIFO
NOT TXPKTRDY
EMPTY
R/W-0-1h R/W-0-1h
SPRUGX9 – 15 April 2011
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