Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1958

Registers
20.9.6.2.7 Control Status Register for Peripheral Receive Endpoint (USBn_PERI_RXCSR)
The control status register for peripheral receive endpoint (USBn_PERI_RXCSR) is a 16-bit register
that provides control and status bits for transfers through the currently-selected Tx endpoint when
controller assumes the role of a peripheral. There is a RXCSR register for each configured Rx endpoint
(not including endpoint 0).
The control status register for peripheral receive endpoint is shown in
Table 20-179.
Figure 20-162. Control Status Register for Peripheral Receive Endpoint (USBn_PERI_RXCSR)
15 14
AUTOCLEAR ISO
R/W-0-1h R/W-0-1h
7 6
CLRDATATOG SENTSTALL
W-0-1h R/W-0-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-179. Control Status Register for Peripheral Receive Endpoint (USBn_PERI_RXCSR)
Bit Field
15 AUTOCLEAR
14 ISO
13 DMAEN
12 DISNYET
11 DMAMODE
10 DATATOGWREN
9 DATATOG
8 Reserved
7 CLRDATATOG
6 SENTSTALL
5 SENDSTALL
4 FLUSHFIFO
3 DATAERROR
2 OVERRUN
1 FIFOFULL
1958 Universal Serial Bus (USB)
Preliminary
13 12
DMAEN DISNYET
R/W-0-1h R/W-0-1h
5 4
SENDSTALL FLUSHFIFO
R/W-0-1h W-0-1h
Field Descriptions
Description
DMA Mode: The CPU sets the AUTOCLEAR bit prior to enabling the Rx DMA. CPU Mode: If
the CPU sets the AUTOCLEAR bit, then the RXPKTRDY bit will be automatically cleared
when a packet of RXMAXP bytes has been unloaded from the Receive FIFO. When packets
of less than the maximum packet size are unloaded, RXPKTRDY will have to be cleared
manually.
Set this bit to enable the Receive endpoint for Isochronous transfers, and clear it to enable
the Receive endpoint for bulk/interrupt transfers.
Set this bit to enable the DMA request for the Receive endpoints.
DISNYET: Applies only for bulk/interrupt transactions: The CPU sets this bit to disable the
sending of NYET handshakes. When set, all successfully received Rx packets are ACK'd
including at the point at which the FIFO becomes full. Note: This bit only has any effect in
high-speed mode, in which mode it should be set for all Interrupt endpoints. PID_ERROR:
Applies only for ISO Transactions: The core sets this bit to indicate a PID error in the
received packet.
Always clear this bit to 0.
Write 1 to this bit to enable the DATATOG bit to be written. This bit is automatically cleared
once the new value is written to DATATOG.
When read, this bit indicates the current state of the Receive EP data toggle. If
DATATOGWREN is high, this bit can be written with the required setting of the data toggle. If
DATATOGWREN is low, any value written to this bit is ignored.
Reserved
Write a 1 to this bit to reset the endpoint data toggle to 0.
This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the
TXPKTRDY bit is cleared. You should clear this bit.
Write a 1 to this bit to issue a STALL handshake. Clear this bit to terminate the stall condition.
Note: This bit has no effect where the endpoint is being used for Isochronous transfers.
Write a 1 to this bit to flush the next packet to be read from the endpoint Receive FIFO. The
FIFO pointer is reset and the RXPKTRDY bit is cleared. Note: FLUSHFIFO has no effect
unless RXPKTRDY is set. Also note that, if the FIFO is double-buffered, FLUSHFIFO may
need to be set twice to completely clear the FIFO.
This bit is set when RXPKTRDY is set if the data packet has a CRC or bit-stuff error. It is
cleared when RXPKTRDY is cleared. Note: This bit is only valid when the endpoint is
operating in ISO mode. In Bulk mode, it always returns zero.
This bit is set if an OUT packet cannot be loaded into the Receive FIFO. You should clear
this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In bulk mode,
it always returns zero.
This bit is set when no more packets can be loaded into the Receive FIFO.
© 2011, Texas Instruments Incorporated
Figure 20-162
11 10
DATA
DMAMODE
TOGWREN
R/W-0-1h W-0-1h
3 2
DATAERROR OVERRUN
R-0-1h R/W-0-1h
www.ti.com
and described in
9 8
DATATOG Reserved
R/W-0-1h R-0h
1 0
FIFOFULL RXPKTRDY
R-0-1h R/W-0-1h
SPRUGX9 – 15 April 2011
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