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20.9.6.2.4 Control Status Register for Peripheral Transmit Endpoint (USBn_PERI_TXCSR)
The control status register for peripheral transmit endpoint (USBn_PERI_TXCSR) is a 16-bit register
that provides control and status bits for transfers through the currently-selected Tx endpoint when
controller assumes the role of a peripheral. There is a TXCSR register for each configured Tx endpoint
(not including Endpoint 0).
The control status register for peripheral transmit endpoint is shown in
Table
20-176.
Figure 20-159. Control Status Register for Peripheral Transmit Endpoint (USBn_PERI_TXCSR)
15
14
AUTOSET
ISO
R/W-0-1h
R/W-0-1h
7
6
Reserved
CLRDATATOG
R-0h
W-0-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-176. Control Status Register for Peripheral Transmit Endpoint (USBn_PERI_TXCSR)
Bits
Field Name
15
AUTOSET
14
ISO
13
MODE
12
DMAEN
11
FRCDATATOG
10
DMAMODE
7
Reserved
6
CLRDATATOG
5
SENTSTALL
4
SENDSTALL
3
FLUSHFIFO
2
UNDERRUN
1
FIFONOTEMPTY
0
TXPKTRDY
SPRUGX9 – 15 April 2011
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Preliminary
13
12
MODE
DMAEN
R/W-0-1h
R/W-0-1h
5
4
SENTSTALL
SENDSTALL
R/W-0-1h
R/W-0-1h
Field Descriptions
Description
DMA Mode: The CPU needs to set the AUTOSET bit prior to enabling the Tx DMA. CPU
Mode: If the CPU sets the AUTOSET bit, the TXPKTRDY bit will be automatically set when
data of the maximum packet size (value in TXMAXP) is loaded into the Tx FIFO. If a packet
of less than the maximum packet size is loaded, then the TXPKTRDY bit will have to be set
manually.
Set this bit to enable the Tx endpoint for Isochronous transfers, and clear it to enable the
Tx endpoint for Bulk or Interrupt transfers.
Set this bit to enable the endpoint direction as Tx, and clear the bit to enable it as Rx. Note:
This bit has any effect only where the same endpoint FIFO is used for both Transmit and
Receive transactions.
Set this bit to enable the DMA request for the Tx endpoint.
Set this bit to force the endpoint data toggle to switch and the data packet to be cleared
from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt
Tx endpoints that are used to communicate rate feedback for Isochronous endpoints.
This bit should always be set to 1 when the DMA is enabled.
Reserved
Write a 1 to this bit to reset the endpoint data toggle to 0.
This bit is set automatically when a STALL handshake is transmitted. The FIFO is flushed
and the TXPKTRDY bit is cleared. You should clear this bit.
Write a 1 to this bit to issue a STALL handshake to an IN token. Clear this bit to terminate
the stall condition. Note: This bit has no effect where the endpoint is being used for
Isochronous transfers.
Write a 1 to this bit to flush the next packet to be transmitted from the endpoint Tx FIFO.
The FIFO pointer is reset and the TXPKTRDY bit is cleared. Note: FlushFIFO has no effect
unless the TXPKTRDY bit is set. Also note that, if the FIFO is double-buffered, FlushFIFO
may need to be set twice to completely clear the FIFO.
This bit is set automatically if an IN token is received when TXPKTRDY is not set. You
should clear this bit.
This bit is set when there is at least 1 packet in the Tx FIFO. You should clear this bit.
Set this bit after loading a data packet into the FIFO. It is cleared automatically when a
data packet has been transmitted. An interrupt is generated (if enabled) when the bit is
cleared.
© 2011, Texas Instruments Incorporated
Figure 20-159
11
10
FRCDATATOG
DMAMODE
R/W-0-1h
R/W-0-1h
3
2
FLUSHFIFO
UNDERRUN
R/W-0-1h
R/W-0-1h
Registers
and described in
9
8
1
0
FIFO
NOT
TXPKTRDY
EMPTY
R/W-0-1h
R/W-0-1h
1955
Universal Serial Bus (USB)
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