Ddr2/Mddr Memory Controller Clocking - Texas Instruments AM1802 Reference Manual

Arm microprocessor system
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Peripheral Clocking

6.3.2 DDR2/mDDR Memory Controller Clocking

The DDR2/mDDR memory controller requires two input clocks to source VCLK and 2X_CLK (see
Figure
6-3):
VCLK is sourced from PLL0_SYSCLK2/2 that clocks the command FIFO, write FIFO, and read FIFO of
the DDR2/mDDR memory controller. From this, VCLK drives the interface to the peripheral bus.
2X_CLK is sourced from PLL1_SYSCLK1.
2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
Table 6-5
shows example PLL register settings based on the OSCIN reference clock frequency of
25 MHz. From these example configurations, the following observations are made:
To achieve the maximum frequency (150 MHz) supported by the DDR2/mDDR memory controller and
the typical CPU frequency of 300 MHz, the output of the PLL multiplier should be set to be 300 MHz
and the DDR_CLK source should be set to PLL1_SYSCLK1.
The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier
block.
The PLLDIV1 block that sets the divider ratio for SYSCLK1 can be changed to achieve various clock
frequencies.
For certain PLL1 multiplier and PLL1 post-divider control register (POSTDIV) settings, a higher clock
frequency can be achieved by selecting SYSCLK1 as the clock source for 2X_CLK.
If the DDR2/mDDR memory controller is not in use and the DDR_CLK and DDR_CLK are used in the
application as a free running clock that could be used by an FPGA or for some other purpose, then
2X_CLK should be used as the source for DDR_CLK and DDR_CLK and VCLK should be gated off. This
allows clock gating of the majority of the logic in the DDR2/mDDR memory controller via the LPSC while
still providing a clock on the DDR_CLK and DDR_CLK.
NOTE: DDR_CLK and DDR_CLK are output clock signals.
64
Device Clocking
Copyright © 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX5A – May 2011
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