Power And Sleep Controller (Psc) - Texas Instruments AM1808 User Manual

www.ti.com
6.8

Power and Sleep Controller (PSC)

The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Supports IcePick emulation features: power, clock and reset
PSC0 controls 16 local PSCs.
PSC1 controls 32 local PSCs.
PSC0 BYTE
ADDRESS
0x01C1 0000
0x01C1 0018
0x01C1 0040
0x01C1 0050
0x01C1 0060
0x01C1 0068
0x01C1 0120
0x01C1 0128
0x01C1 0200
0x01C1 0204
0x01C1 0300
0x01C1 0304
0x01C1 0400
0x01C1 0404
0x01C1 0800
0x01C1 0804
0x01C1 0808
0x01C1 080C
0x01C1 0810
0x01C1 0814
0x01C1 0818
0x01C1 081C
0x01C1 0820
0x01C1 0824
0x01C1 0828
0x01C1 082C
0x01C1 0830
0x01C1 0834
Copyright © 2010–2014, Texas Instruments Incorporated
Table 6-8. Power and Sleep Controller (PSC) Registers
PSC1 BYTE
ACRONYM
ADDRESS
0x01E2 7000 REVID
0x01E2 7018 INTEVAL
0x01E2 7040 MERRPR0
0x01E2 7050 MERRCR0
0x01E2 7060 PERRPR
0x01E2 7068 PERRCR
0x01E2 7120 PTCMD
0x01E2 7128 PTSTAT
0x01E2 7200 PDSTAT0
0x01E2 7204 PDSTAT1
0x01E2 7300 PDCTL0
0x01E2 7304 PDCTL1
0x01E2 7400 PDCFG0
0x01E2 7404 PDCFG1
0x01E2 7800 MDSTAT0
0x01E2 7804 MDSTAT1
0x01E2 7808 MDSTAT2
0x01E2 780C MDSTAT3
0x01E2 7810 MDSTAT4
0x01E2 7814 MDSTAT5
0x01E2 7818 MDSTAT6
0x01E2 781C MDSTAT7
0x01E2 7820 MDSTAT8
0x01E2 7824 MDSTAT9
0x01E2 7828 MDSTAT10
0x01E2 782C MDSTAT11
0x01E2 7830 MDSTAT12
0x01E2 7834 MDSTAT13
Submit Documentation Feedback
Product Folder Links:
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
REGISTER DESCRIPTION
Peripheral Revision and Class Information Register
Interrupt Evaluation Register
Module Error Pending Register 0 (module 0-15) (PSC0)
Module Error Pending Register 0 (module 0-31) (PSC1)
Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
Power Error Pending Register
Power Error Clear Register
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain 0 Status Register
Power Domain 1 Status Register
Power Domain 0 Control Register
Power Domain 1 Control Register
Power Domain 0 Configuration Register
Power Domain 1 Configuration Register
Module 0 Status Register
Module 1 Status Register
Module 2 Status Register
Module 3 Status Register
Module 4 Status Register
Module 5 Status Register
Module 6 Status Register
Module 7 Status Register
Module 8 Status Register
Module 9 Status Register
Module 10 Status Register
Module 11 Status Register
Module 12 Status Register
Module 13 Status Register
Peripheral Information and Electrical Specifications
AM1808
AM1808
87