Mpu Private Peripherals; Dsp Private Peripherals - Texas Instruments OMAP5912 Reference Manual

Table 1.

MPU Private Peripherals

Peripheral Name
MPU level 2 interrupt handler
32-kHz watchdog
Secure watchdog
ULPD
CompactFlash controller
RNG
DES/3DES
SHA−1/MD5
GDMA handler
OMAP5912 configuration
LCDCONV
Table 2.

DSP Private Peripherals

Peripheral Name
DSP DMA handler
DSP level 2.1 interrupt
handler
SPRU748A
Table 1 through Table 8 describe the OMAP5912 top-level partitioning. For
more detail on the OMAP5912 core, see Chapter 2, OMAP3.2 Subsystem.
General Description
There is one MPU interrupt handler outside the OMAP 3.2 gigacell. It
supports up to 128 interrupt lines. Both IRQ and FIQ are connected to MPU
interrupt handler level 1.
A general-purpose timer with watchdog functionality clocked at 32 kHz
Same watchdog module used for security and clocked differently
System clock and reset module. Manages the idle mode, generates main
reset to OMAP. Some peripherals clock through its APLL output to generate
the OMAP input system clock.
This module interfaces with the NOR flash memory to enable CompactFlash
card support.
Random number generator module
Data encryption standard and triple DES
Secure module that supports SHA−1 and MD5 secure hash algorithm
64 DMA requests are multiplexed to generate 31 DMA request lines to the
system DMA.
Controls the various configurations of the OMAP5912 functions (I/O
functions, debug functions, clock control, security control register)
Enables conversion of the OMAP LCD 16-bit data bits into 18-bit data bits
General Description
DMA requests are multiplexed to generate 19 DMA request lines to the DSP
DMA.
There is one DSP interrupt handler outside the OMAP 3.2 gigacell. It
supports up to 64 interrupt lines. Only IRQ is connected to the DSP level 1
interrupt handler. The DSP interrupt handler module is derived from the MPU
interrupt handler module.
OMAP5912 Description
Introduction 21