Compactflash Interface - Texas Instruments OMAP5912 Reference Manual

CompactFlash Controller
Figure 5.

CompactFlash Interface

OMAP3.2
Compact Flash and to
common flash memory.
EMIFS
Note: The CompactFlash controller can only be used when the system clock frequency is 12 MHz.
Frame Adjustment Counter (FAC)
Light Pulse Generator (LPG)
SHA-1/MD5 Accelerator
SPRU748A
The CompactFlash controller interfaces a CompactFlash module and a
classical memory interface. Control signals from the memory interface are
processed through the CompactFlash controller to drive the CompactFlash
module, and control signals from CompactFlash are processed to perform a
data transfer to the memory interface. Some pins are shared with common
flash memory, such as address bus, data bus, and control pins. The
CompactFlash controller includes a bypass mode used when common flash
memory, rather than a CompactFlash card, is connected.
The CompactFlash is connected on the EMIFS port of the OMAP3.2 gigacell.
OMAP5912
Controls signals to
The FAC consists of a frame synchronization capture pin (intended to count
the number of rising edges of a frame synchronization signal from a
synchronous serial port) and a frame start capture pin (intended to count the
number of rising edges of a USB frame start signal). The respective count
values can then be used by system software to adjust the duration of the two
time domains with respect to each other in order to reduce the overflow and
underflow.
The FAC module is used to control the number of McBSP2 and USB frames.
The LPG module is used to control the blinking period of an external LED.
The SHA-1/MD5 security module provides hardware-accelerated hash
functions. It can run either the SHA-1 algorithm in compliance with FIPS 180-1
standard or the MD5 message-digest algorithm developed by Rivest.
CompactFlash
controller
Part of the interface is common
OMAP5912 Description
Classical flash
memory
CompactFlash
to both memories, other part is
dedicated to CompactFlash or
common memory flash.
Introduction
card
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