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0.1uF,0603,50V,10%,X7R
0.47uF,0805,50V,10%,X7R
5V
RS232 VCC
R13
0,0603,1/8W,5%
C26
C27
100uF,SMT,35V,20%,AL
GND_UART
1uF,0603,25V,10%,X7R
GND_UART
R11
TXD
10.0k,0603,1/10W,5%
spacer
spacer
SDO
SCLK
CS
SDI
CS_SOCKET
LIN EN
5V
SLDU007C – March 2012 – Revised November 2015
Submit Documentation Feedback
U4
2
C1+
V+
C23
4
C1-
V-
5
C2+
C25
TIN
6
C2-
ROUT
16
~FORCEOFF
15
VCC
TOUT (RS232)
RIN (RS232)
C28
~INVALID
12
FORCEON
EN
14
GND
MAX3221EUE+
GND_UART
tssop footprint and P/N
0.1uF,0603,50V,10%,X7R
L1
BEAD
GND
GND_UART
5V
Figure 20. Schematic, RS232
IO-MISO
1
MISO, SDA
IO-SCLK
3
SCLK, SCL
IO-CS
5
CS (SS)
IO-MOSI
7
MOSI
IO-11
9
IO-11
IO-0
11
IO-0
IO-2
13
IO-2
IO-4
15
IO-4
IO-6
17
IO-6
V_5.0_WORLD
19
V_5.0V (OUT)
IO-OSC
21
CHIP OSC (OUT)
V_3.3_WORLD
23
V_3.3V (OUT)
V_DVM_1
25
DVM-1
V_DVM_2
27
DVM-2
V_DVM_3
29
DVM-3
TIGER - A
Figure 21. Schematic, USB Controller
Copyright © 2012–2015, Texas Instruments Incorporated
PGA450Q1EVM Schematics and Layout Drawings
C22
0.47uF,0805,50V,10%,X7R
3
GND_UART
C24
0.47uF,0805,50V,10%,X7R
7
GND_UART
11
TXD
9
RXD
13
TX_232
8
RX_232
Tx
Rx
10
~INVALID
1
GND_UART
2
GND
GND
4
GND
GND
6
GND
GND
8
GND
GND
10
IO-8__TX
IO-8, TX
12
IO-1
IO-1
14
IO-3
TIGER - A
IO-3
16
IO-5
IO-5
18
IO-7
IO-7
20
IO-9__RX
IO-9, RX
22
PWR-DWN
PWR-DWN
24
IO-10
(SLOW OSC)
IO-10 (PIC OSC)
26
IO-A
IO-A
28
IO-B
IO-B
30
DAC_OUT
IO-DAC
J1
5
GND_UART
9
4
8
10
3
RX_232
7
11
2
TX_232
6
1
D Connector 9
LIN TxD
LIN RxD
VPWR
PGA450Q1EVM User's Guide
23
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